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| 型号： | COP8SGA040N9 |
| 厂商： | National Semiconductor Corporation |
| 英文描述： | 8-Bit CMOS ROM Based and OTP Microcontrollers with 8k to 32k Memory, Two Comparators and USART |
| 中文描述： | 8位的CMOS基于ROM和OTP微控制器具有8K到32K的内存，2个比较器和USART |
| 文件页数： | 25/62页 |
| 文件大小： | 913K |
| 代理商： | COP8SGA040N9 |
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7.0 Power Saving Features
Today, the proliferation of battery-operated based applica-
tions has placed new demands on designers to drive power
consumption down. Battery-operated systems are not the
only type of applications demanding low power. The power
budget constraints are also imposed on those consumer/
industrial applications where well regulated and expensive
power supply costs cannot be tolerated. Such applications
rely on low cost and low power supply voltage derived di-
rectly from the “mains” by using voltage rectifier and passive
components. Low power is demanded even in automotive
applications, due to increased vehicle electronics content.
This is required to ease the burden from the car battery. Low
power 8-bit microcontrollers supply the smarts to control
battery-operated, consumer/industrial, and automotive appli-
cations.
Each device offers system designers a variety of low-power
consumption features that enable them to meet the demand-
ing requirements of today’s increasing range of low-power
applications. These features include low voltage operation,
low current drain, and power saving features such as HALT,
IDLE, and Multi-Input wakeup (MIWU).
Each device offers the user two power save modes of op-
eration: HALT and IDLE. In the HALT mode, all microcontrol-
ler activities are stopped. In the IDLE mode, the on-board
oscillator circuitry and timer T0 are active but all other micro-
controller activities are stopped. In either mode, all on-board
RAM, registers, I/O states, and timers (with the exception of
T0) are unaltered.
Clock Monitor, if enabled, can be active in both modes.
7.1 HALT MODE
Each device can be placed in the HALT mode by writing a “1”
to the HALT flag (G7 data bit). All microcontroller activities,
including the clock and timers, are stopped. The WATCH-
DOG logic on the devices are disabled during the HALT
mode. However, the clock monitor circuitry, if enabled, re-
mains active and will cause the WATCHDOG output pin
(WDOUT) to go low. If the HALT mode is used and the user
does not want to activate the WDOUT pin, the Clock Monitor
should be disabled after the devices come out of reset
(resetting the Clock Monitor control bit with the first write to
the WDSVR register). In the HALT mode, the power require-
ments of the devices are minimal and the applied voltage
(V
) may be decreased to V
r
(V
r
= 2.0V) without altering the
state of the machine.
Each device supports three different ways of exiting the
HALT mode. The first method of exiting the HALT mode is
with the Multi-Input Wakeup feature on Port L. The second
method is with a low to high transition on the CKO (G7) pin.
This method precludes the use of the crystal clock configu-
ration (since CKO becomes a dedicated output), and so may
only be used with an R/C clock configuration. The third
method of exiting the HALT mode is by pulling the RESET
pin low.
On wakeup from G7 or Port L, the devices resume execution
from the HALT point. On wakeup from RESET execution will
resume from location PC=0 and all RESET conditions apply.
If a crystal or ceramic resonator may be selected as the
oscillator, the Wakeup signal is not allowed to start the chip
running immediately since crystal oscillators and ceramic
resonators have a delayed start up time to reach full ampli-
tude and frequency stability. The IDLE timer is used to
generate a fixed delay to ensure that the oscillator has
indeed stabilized before allowing instruction execution. In
this case, upon detecting a valid Wakeup signal, only the
oscillator circuitry is enabled. The IDLE timer is loaded with
a value of 256 and is clocked with the t
instruction cycle
clock. The t
clock is derived by dividing the oscillator clock
down by a factor of 9. The Schmitt trigger following the CKI
inverter on the chip ensures that the IDLE timer is clocked
only when the oscillator has a sufficiently large amplitude to
meet the Schmitt trigger specifications. This Schmitt trigger
is not part of the oscillator closed loop. The start-up time-out
from the IDLE timer enables the clock signals to be routed to
the rest of the chip.
If an R/C clock option is being used, the fixed delay is
introduced optionally. A control bit, CLKDLY, mapped as
configuration bit G7, controls whether the delay is to be
introduced or not. The delay is included if CLKDLY is set,
and excluded if CLKDLY is reset. The CLKDLY bit is cleared
on reset.
Each device has two options associated with the HALT
mode. The first option enables the HALT mode feature, while
the second option disables the HALT mode selected through
bit 0 of the ECON register. With the HALT mode enable
option, the device will enter and exit the HALT mode as
described above. With the HALT disable option, the device
cannot be placed in the HALT mode (writing a “1” to the
HALT flag will have no effect, the HALT flag will remain “0”).
The WATCHDOG detector circuit is inhibited during the
HALT mode. However, the clock monitor circuit if enabled
remains active during HALT mode in order to ensure a clock
monitor error if the device inadvertently enters the HALT
mode as a result of a runaway program or power glitch.
If the device is placed in the HALT mode, with the R/C
oscillator selected, the clock input pin (CKI) is forced to a
logic high internally. With the crystal or external oscillator the
CKI pin is TRI-STATE.
It is recommended that the user not halt the device by merely
stopping the clock in external oscillator mode. If this method
is used, there is a possibility of greater than specified HALT
current.
If the user wishes to stop an external clock, it is recom-
mended that the CPU be halted by setting the Halt flag first
and the clock be stopped only after the CPU has halted.
C
www.national.com
25
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| COP8SGA040Q6 | 8-Bit CMOS ROM Based and OTP Microcontrollers with 8k to 32k Memory, Two Comparators and USART |
| COP8SGA040Q7 | 8-Bit CMOS ROM Based and OTP Microcontrollers with 8k to 32k Memory, Two Comparators and USART |
| COP8SGA040Q8 | 8-Bit CMOS ROM Based and OTP Microcontrollers with 8k to 32k Memory, Two Comparators and USART |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| COP8SGA040Q3 | 制造商:NSC 制造商全称:National Semiconductor 功能描述:8-Bit CMOS ROM Based and OTP Microcontrollers with 8k to 32k Memory, Two Comparators and USART |
| COP8SGA040Q6 | 制造商:NSC 制造商全称:National Semiconductor 功能描述:8-Bit CMOS ROM Based and OTP Microcontrollers with 8k to 32k Memory, Two Comparators and USART |
| COP8SGA040Q7 | 制造商:NSC 制造商全称:National Semiconductor 功能描述:8-Bit CMOS ROM Based and OTP Microcontrollers with 8k to 32k Memory, Two Comparators and USART |
| COP8SGA040Q8 | 制造商:NSC 制造商全称:National Semiconductor 功能描述:8-Bit CMOS ROM Based and OTP Microcontrollers with 8k to 32k Memory, Two Comparators and USART |
| COP8SGA040Q9 | 制造商:NSC 制造商全称:National Semiconductor 功能描述:8-Bit CMOS ROM Based and OTP Microcontrollers with 8k to 32k Memory, Two Comparators and USART |
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