CS7410
22
DS553PP1
sor communication
Three 32-bit timers for I/O and other uses, with
programmable interval rates
“Getbits” module accelerates peripheral stream
parsing
Both hardware and software interrupts on data
or debug
2.2.4
Memory System
Large internal SRAM (80 Kbyte) and internal
program ROM (256 Kbyte)
Supports both Synchronous and EDO DRAM
(256 KBytes to 8 MBytes) for ESP
Supports one bank of FLASH and ROM (up to
2 MBytes) for nonvolatile storage
4-, 8-, or16-bit data bus for DRAM, 8-bit data
bus for ROM
2.2.5
CD Interface
Glueless interfaces to CD servo chip set, sup-
porting all standard CD formats
Includes pattern matching hardware to support
fast ESP recovery
2.2.6
Audio Interface
Supports 4 channels PCM, I
2
S connectivity at
up to 24 bits
Flexible audio clocking scheme using internal
PLL and dividers, or external pins
Simultaneous IEC-958 output with program-
mable channel status and user data
Integrated sigma-delta (
Σ
) stereo audio mod-
ulator
2.2.7
External Interface
2-wire serial slave port, used for debug
3- or 4-wire synchronous serial master/slave
port for external controller or slave peripheral
Separate synchronous serial master port opti-
mized for receiving CD sub-codes
Up to 29 programmable bi-directional I/O
(GPIO) and up to 9 output only (GPO) pins
(some multiplexed with other peripherals)
All pins defined as GPIOs can be used to re-
ceive edge or level detection interrupts.
Pulse-width modulated (PWM) output pin can
be used to create simple ADC using low-cost
comparator (i.e., for battery voltage monitor)
2.2.8
System Functions
Internal oscillator uses external crystal, or re-
ceives clock (i.e. 16.9 MHz) from CD servo
Internal PLL generates any system clock fre-
quency, chip can run up to 90 MHz
Includes clock divider and clock shutoff cir-
cuits for low power/sleep modes
Advanced 0.18 micron CMOS technology,
runs off 1.8 V and 3.3 V
All I/O pins are 3.3 V, with 5 V tolerance
100-pin MQFP package
100-pin LQFP package