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参数资料
型号： CY7C1487V25-133BGI
厂商： CYPRESS SEMICONDUCTOR CORP
元件分类： DRAM
英文描述： 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM
中文描述： 1M X 72 CACHE SRAM, 6.5 ns, PBGA209
封装： 14 X 22 MM, 1.76 MM HEIGHT, FBGA-209
文件页数： 19/30页
文件大小： 1028K
代理商： CY7C1487V25-133BGI
CY7C1481V25
CY7C1483V25
CY7C1487V25
Document #: 38-05281 Rev. *H
Page 19 of 30
Maximum Ratings
Exceeding the maximum ratings may impair the useful life of
the device. These user guidelines are not tested.
Storage Temperature .................................–65
°
C to +150
°
C
Ambient Temperature with
Power Applied.............................................–55
°
C to +125
°
C
Supply Voltage on V
DD
Relative to GND........–0.3V to +3.6V
Supply Voltage on V
DDQ
Relative to GND ......–0.3V to +V
DD
DC Voltage Applied to Outputs
in Tri-State........................................... –0.5V to V
DDQ
+ 0.5V
DC Input Voltage....................................–0.5V to V
DD
+ 0.5V
Electrical Characteristics
Over the Operating Range
[13, 14]
Current into Outputs (LOW).........................................20 mA
Static Discharge Voltage........................................... >2001V
(MIL-STD-883, Method 3015)
Latch Up Current.................................................... >200 mA
Operating Range
Range
Ambient
Temperature
0°C to +70°C
–40°C to +85°C
V
DD
V
DDQ
Commercial
Industrial
2.5V
–5%/+5% 1.7V to
V
DD
Parameter
V
DD
V
DDQ
Description
Power Supply Voltage
IO Supply Voltage
Test Conditions
Min
2.375
2.375
1.7
2.0
1.6
Max
2.625
V
DD
1.9
Unit
V
V
V
V
V
V
V
V
V
V
V
μ
A
for 2.5V IO
for 1.8V IO
for 2.5V IO, I
OH
= –1.0 mA
for 1.8V IO, I
OH
= –100
μ
A
for 2.5V IO, I
OL
= 1.0 mA
for 1.8V IO, I
OL
= 100
μ
A
for 2.5V IO
for 1.8V IO
for 2.5V IO
for 1.8V IO
GND
≤
V
I
≤
V
DDQ
V
OH
Output HIGH Voltage
V
OL
Output LOW Voltage
0.4
0.2
V
IH
Input HIGH Voltage
[13]
1.7
1.26
–0.3
–0.3
–5
V
DD
+ 0.3V
V
DD
+ 0.3V
0.7
0.36
5
V
IL
Input LOW Voltage
[13]
I
X
Input Leakage Current
except ZZ and MODE
Input Current of MODE Input = V
SS
–30
μ
A
μ
A
μ
A
μ
A
μ
A
mA
mA
mA
mA
Input = V
DD
Input = V
SS
Input = V
DD
5
Input Current of ZZ
–5
30
5
305
275
170
170
I
OZ
I
DD
Output Leakage Current GND
≤
V
I
≤
V
DDQ,
Output Disabled
V
DD
Operating Supply
Current
f = f
MAX
= 1/t
CYC
–5
V
DD
= Max., I
OUT
= 0 mA,
7.5 ns cycle, 133 MHz
10 ns cycle, 100 MHz
7.5 ns cycle, 133 MHz
10 ns cycle, 100 MHz
I
SB1
Automatic CE
Power Down
Current—TTL Inputs
Automatic CE
Power Down
Current—CMOS Inputs
Automatic CE
Power Down
Current—CMOS Inputs
Automatic CE
Power Down
Current—TTL Inputs
Max. V
DD
, Device Deselected,
V
IN
≥
V
IH
or V
IN
≤
V
IL
, f = f
MAX,
inputs switching
Max. V
DD
, Device Deselected,
V
IN
≥
V
DD
– 0.3V or V
IN
≤
0.3V,
f = 0, inputs static
Max. V
DD
, Device Deselected,
V
IN
≥
V
DDQ
– 0.3V or V
IN
≤
0.3V,
f = f
MAX
, inputs switching
Max. V
DD
, Device Deselected,
V
IN
≥
V
DD
– 0.3V or V
IN
≤
0.3V,
f = 0, inputs static
I
SB2
All speeds
120
mA
I
SB3
7.5 ns cycle, 133 MHz
10 ns cycle, 100 MHz
170
170
mA
mA
I
SB4
All Speeds
135
mA
Notes
13.Overshoot: V
(AC) < V
+ 1.5V (Pulse width less than t
/2), undershoot: V
(AC) > –2V (Pulse width less than t
CYC
/2).
14.T
Power-up
: Assumes a linear ramp from 0V to V
DD
(min.) within 200 ms. During this time V
IH
< V
DD
and V
DDQ
< V
DD
.
[+] Feedback
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