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参数资料
| 型号： | CY7C1487V25-133BGI |
| 厂商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分类： | DRAM |
| 英文描述： | 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM |
| 中文描述： | 1M X 72 CACHE SRAM, 6.5 ns, PBGA209 |
| 封装： | 14 X 22 MM, 1.76 MM HEIGHT, FBGA-209 |
| 文件页数： | 9/30页 |
| 文件大小： | 1028K |
| 代理商： | CY7C1487V25-133BGI |
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CY7C1481V25
CY7C1483V25
CY7C1487V25
Document #: 38-05281 Rev. *H
Page 9 of 30
Functional Overview
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. Maximum access delay from
the clock rise (t
CDV
) is 6.5 ns (133-MHz device).
The CY7C1481V25/CY7C1483V25/CY7C1487V25 supports
secondary cache in systems using either a linear or inter-
leaved burst sequence. The interleaved burst order supports
Pentium and i486 processors. The linear burst sequence is
suited for processors that use a linear burst sequence. The
burst order is user selectable, and is determined by sampling
the MODE input. Accesses can be initiated with either the
Processor Address Strobe (ADSP) or the Controller Address
Strobe (ADSC). Address advancement through the burst
sequence is controlled by the ADV input. A two-bit on-chip
wraparound burst counter captures the first address in a burst
sequence and automatically increments the address for the
rest of the burst access.
Byte write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BW
X
) inputs. A Global Write
Enable (GW) overrides all byte write inputs and writes data to
all four bytes. All writes are simplified with on-chip
synchronous self-timed write circuitry.
Three synchronous Chip Selects (CE
1
, CE
2
, CE
3[1]
) and an
asynchronous Output Enable (OE) provide easy bank
selection and output tri-state control. ADSP is ignored if CE
1
is HIGH.
Single Read Accesses
A single read access is initiated when the following conditions
are satisfied at clock rise: (1) CE
1
, CE
2
, and CE
3[1]
are all
asserted active, and (2) ADSP or ADSC is asserted LOW (if
the access is initiated by ADSC, the write inputs must be
deasserted during this first cycle). The address presented to
the address inputs is latched into the address register and the
burst counter/control logic and presented to the memory core.
If the OE input is asserted LOW, the requested data is
available at the data outputs a maximum of t
CDV
after clock
rise. ADSP is ignored if CE
1
is HIGH.
Single Write Accesses Initiated by ADSP
This access is initiated when the following conditions are
satisfied at clock rise: (1) CE
1
, CE
2
, CE
3[1]
are all asserted
active, and (2) ADSP is asserted LOW. The addresses
presented are loaded into the address register and the burst
inputs (GW, BWE, and BW
X
) are ignored during this first clock
cycle. If the write inputs are asserted active on the next clock
rise, the appropriate data is latched and written into the device.
The device allows byte writes. All IOs are tri-stated during a
byte write. Because this is a common IO device, the
asynchronous OE input signal must be deasserted and the IOs
must be tri-stated prior to the presentation of data to DQs. As
a safety precaution, the data lines are tri-stated after a write
cycle is detected, regardless of the state of OE.
Single Write Accesses Initiated by ADSC
This write access is initiated when the following conditions are
satisfied at clock rise: (1) CE
1
, CE
2
, and CE
3[1]
are all asserted
active, (2) ADSC is asserted LOW, (3) ADSP is deasserted
HIGH, and (4) the write input signals (GW, BWE, and BW
X
)
indicate a write access. ADSC is ignored if ADSP is active
LOW.
The addresses presented are loaded into the address register
and the burst counter/control logic and delivered to the
memory core. The information presented to DQ
S
is written into
the specified address location. The device allows byte writes.
All IOs are tri-stated when a write is detected, even a byte
write. Because this is a common IO device, the asynchronous
OE input signal must be deasserted and the IOs must be
tri-stated before the presentation of data to DQs. As a safety
precaution, the data lines are tri-stated after a write cycle is
detected, regardless of the state of OE.
Burst Sequences
The CY7C1481V25/CY7C1483V25/CY7C1487V25 provides
an on-chip two-bit wraparound burst counter inside the SRAM.
The burst counter is fed by A
[1:0]
, and can follow either a linear
or interleaved burst order. The burst order is determined by the
state of the MODE input. A LOW on MODE selects a linear
burst sequence. A HIGH on MODE selects an interleaved
burst order. Leaving MODE unconnected causes the device to
default to an interleaved burst sequence.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE
1
, CE
2
, CE
3[1]
, ADSP, and ADSC must
remain inactive for the duration of t
ZZREC
after the ZZ input
returns LOW.
Interleaved Burst Address Table
(MODE = Floating or V
DD
)
First
Address
A1: A0
A1: A0
00
01
10
11
Second
Address
Third
Address
A1: A0
10
11
00
01
Fourth
Address
A1: A0
11
10
01
00
01
00
11
10
Linear Burst Address Table
(MODE = GND)
First
Address
A1: A0
00
01
10
11
Second
Address
A1: A0
01
10
11
00
Third
Address
A1: A0
10
11
00
01
Fourth
Address
A1: A0
11
00
01
10
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