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参数资料
| 型号： | CY7C4225-15JI |
| 厂商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分类： | DRAM |
| 英文描述： | 64/256/512/1K/2K/4K x18 Low-Voltage Synchronous FIFOs |
| 中文描述： | 1K X 18 OTHER FIFO, 10 ns, PQCC68 |
| 封装： | PLASTIC, LCC-68 |
| 文件页数： | 3/25页 |
| 文件大小： | 409K |
| 代理商： | CY7C4225-15JI |
CY7C4425/4205/4215
CY7C4225/4235/4245
3
Selection Guide
7C42X5-10
100
8
10
3
0.5
8
45
50
7C42X5-15
66.7
10
15
4
1
10
45
50
7C42X5-25
40
15
25
6
1
15
45
50
7C42X5-35
28.6
20
35
7
2
20
45
50
Maximum Frequency (MHz)
Maximum Access Time (ns)
Minimum Cycle Time (ns)
Minimum Data or Enable Set-Up (ns)
Minimum Data or Enable Hold (ns)
Maximum Flag Delay (ns)
Operating Current (I
CC2
)
(mA) @ freq=20MHz
Commercial
Industrial
CY7C4425
64 x 18
68-pin PLCC
64-pin TQFP
(10x10/14x14)
CY7C4205
256 x 18
68-pin PLCC
64-pin TQFP
(10x10/14x14)
CY7C4215
512 x 18
68-pin PLCC
64-pin TQFP
(10x10/14x14)
CY7C4225
1K x 18
68-pin PLCC
64-pin TQFP
(10x10/14x14)
CY7C4235
2K x 18
68-pin PLCC
64-pin TQFP
(10x10/14x14)
CY7C4245
4K x 18
68-pin PLCC
64-pin TQFP
(10x10/14x14)
Density
Packages
Pin Definitions
Signal Name
D
0–17
Q
0–17
WEN
Description
Data Inputs
I/O
I
Function
Data inputs for an 18-bit bus
Data Outputs
O
Data outputs for an 18-bit bus
Write Enable
I
Enables the WCLK input
REN
Read Enable
I
Enables the RCLK input
WCLK
Write Clock
I
The rising edge clocks data into the FIFO when WEN is LOW and the FIFO is not
Full. When LD is asserted, WCLK writes data into the programmable flag-offset
register.
RCLK
Read Clock
I
The rising edge clocks data out of the FIFO when REN is LOW and the FIFO is not
Empty. When LD is asserted, RCLK reads data out of the programmable flag-off-
set register.
WXO/HF
Write Expansion
Out/Half Full Flag
O
Dual-Mode Pin:
Single device or width expansion - Half Full status flag.
Cascaded - Write Expansion Out signal, connected to WXI of next device.
EF
Empty Flag
O
When EF is LOW, the FIFO is empty. EF is synchronized to RCLK.
FF
Full Flag
O
When FF is LOW, the FIFO is full. FF is synchronized to WCLK.
PAE
Programmable
Almost Empty
O
When PAE is LOW, the FIFO is almost empty based on the almost-empty offset
value programmed into the FIFO. PAE is asynchronous when V
CC
/SMODE is tied
to V
CC
; it is synchronized to RCLK when V
CC
/SMODE is tied to V
SS
.
When PAF is LOW, the FIFO is almost full based on the almost full offset value
programmed into the FIFO. PAF is asynchronous when V
CC
/SMODE is tied to
V
CC
; it is synchronized to WCLK when V
CC
/SMODE is tied to V
SS
.
When LD is LOW, D
0 - 17
(O
0 - 17
) are written (read) into (from) the programma-
ble-flag-offset register.
PAF
Programmable
Almost Full
O
LD
Load
I
FL/RT
First Load/
Retransmit
I
Dual-Mode Pin:
Cascaded - The first device in the daisy chain will have FL tied to V
SS
; all other
devices will have FL tied to V
CC
. In standard mode of width expansion, FL is tied
to V
SS
on all devices.
Not Cascaded - Tied to V
SS
. Retransmit function is also available in standalone
mode by strobing RT.
WXI
Write Expansion
Input
I
Cascaded - Connected to WXO of previous device.
Not Cascaded - Tied to V
SS
.
相关PDF资料 |
PDF描述 |
|---|---|
| CY7C4225-25AC | 64/256/512/1K/2K/4K x18 Low-Voltage Synchronous FIFOs |
| CY7C4225-25AI | 64/256/512/1K/2K/4K x18 Low-Voltage Synchronous FIFOs |
| CY7C4225-25ASC | 64/256/512/1K/2K/4K x18 Low-Voltage Synchronous FIFOs |
| CY7C4225-25ASI | 64/256/512/1K/2K/4K x18 Low-Voltage Synchronous FIFOs |
| CY7C4225-25JC | 64/256/512/1K/2K/4K x18 Low-Voltage Synchronous FIFOs |
相关代理商/技术参数 |
参数描述 |
|---|---|
| CY7C422525AC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C4225-25AC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C4225-25JC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C4225V-15ASC | 功能描述:IC SYNC FIFO MEM 1KX18 64LQFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:CY7C 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
| CY7C4225V-15ASXC | 功能描述:先进先出 1K X18 LO VLTG SYNC 先进先出 COM RoHS:否 制造商:IDT 电路数量: 数据总线宽度:18 bit 总线定向:Unidirectional 存储容量:4 Mbit 定时类型:Synchronous 组织:256 K x 18 最大时钟频率:100 MHz 访问时间:10 ns 电源电压-最大:3.6 V 电源电压-最小:6 V 最大工作电流:35 mA 最大工作温度:+ 85 C 封装 / 箱体:TQFP-80 封装: |
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