参数资料
型号: DS1775R2+T&R
厂商: MAXIM INTEGRATED PRODUCTS INC
元件分类: Switch/Digital Output Temperature Sensor
英文描述: DIGITAL TEMP SENSOR-SERIAL, 12BIT(s), 2Cel, RECTANGULAR, SURFACE MOUNT
封装: LEAD FREE, SOT-23, 5 PIN
文件页数: 13/17页
文件大小: 328K
代理商: DS1775R2+T&R
DS1775
5 of 14
Temperature/Data Relationships Table 2
S
26
25
24
23
22
21
20
MSB
MSb
(UNIT =
°C)
LSb
2-1
2-2
2-3
2-4
0
LSB
TEMP
DIGITAL OUTPUT
(Binary)
DIGITAL OUTPUT (Hex)
+125
°C
0111 1101 0000 0000
7D00h
+25.0625
°C
0000 1010 0010 0000
1910h
+10.125
°C
0000 1010 0010 0000
0A20h
+0.5
°C
0000 0000 1000 0000
0080h
+0
°C
0000 0000 0000 0000
0000h
-0.5
°C
1111 1111 1000 0000
FF80h
-10.125
°C
1111 0101 1110 0000
F5E0h
-25.0625
°C
1110 0110 1111 0000
E6F0h
-55
°C
1100 1001 0000 0000
C900h
OPERATION–Thermostat Control
In its comparator operating mode, the DS1775 functions as a thermostat with programmable hysteresis, as
shown in Figure 2. When the DS1775’s temperature meets or exceeds the value stored in the high
temperature trip register (TOS) a consecutive number of times, as defined by the configuration register, the
output becomes active and stays active until the first time that the temperature falls below the temperature
stored in the low temperature trigger register (THYST). In this way, any amount of hysteresis may be
obtained. The DS1775 powers up in the comparator mode with TOS=80
°C and THYST=75°C and can be
used as a standalone thermostat (no 2–wire interface required) with those setpoints.
In the interrupt mode, the O.S. output will first become active following the programmed number of
consecutive conversions above TOS. The fault can only be cleared by either setting the DS1775 in a
shutdown mode or by reading any register (temperature, configuration, TOS, or THYST) on the device.
Following a clear, a subsequent fault can only occur if consecutive conversions fall below THYST. This
interrupt/clear process is thus cyclical (TOS, clear, THYST, clear, TOS, clear, THYST, clear, ...). Only the first
of multiple consecutive TOS violations will activate O.S., even if each fault is separated by a clearing
function. The same situation applies to multiple consecutive THYST events.
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