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| 型号： | DS1236AS-5N |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 2/19页 |
| 文件大小： | 0K |
| 描述： | IC MICROMANAGER 5% IND 16-SOIC |
| 标准包装： | 45 |
| 系列： | MicroManager |
| 类型： | 备用电池电路 |
| 监视电压数目： | 1 |
| 输出： | 开路漏极，推挽式 |
| 复位： | 高有效/低有效 |
| 复位超时： | 最小为 25 ms |
| 电压 - 阀值： | 4.62V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 16-SOIC W |
| 包装： | 管件 |
DS1236
input which is debounced and activates reset outputs. An internal watchdog timer can also force the reset
outputs to the active state if the strobe input is not driven low prior to watchdog timeout. Reset control
and wake-up/sleep control inputs also provide the necessary signals for orderly shutdown and startup in
battery backup and battery operated applications. A block diagram of the DS1236 is shown in Figure 1.
PIN DESCRIPTION
PIN NAME
V BAT
V CCO
V CC
PF
PF
WC/ SC
RC
IN
NMI
ST
CEO
CEI
PBRST
RST
RST
DESCRIPTION
+3V battery input provides nonvolatile operation of control functions.
V CC output for nonvolatile SRAM applications.
+5V primary power input.
Power-fail indicator, active high, used for external power switching as shown in
Figure 9.
Power-fail indicator, active low.
Wake-up and Sleep control. Invokes low-power mode.
Reset control input. Determines reset output. Normally low for NMOS processors and
high for battery backed CMOS processors.
Early warning power-fail input. This voltage sense point can be tied (via resistor
divider) to a user-selected voltage.
Non-maskable interrupt. Used in conjunction with the IN pin to indicate an impending
power failure.
Strobe input. A high-to-low transition will reset the watchdog timer, indicating that
software is still in control.
Chip enable output. Used with nonvolatile SRAM applications.
Chip enable input.
Pushbutton reset input.
Active low reset output.
Active high reset output.
PROCESSOR MODE
A distinction is often made between CMOS and NMOS processor systems. In a CMOS system, power
consumption may be a concern, and nonvolatile operation is possible by battery backing both the SRAM
and the CMOS processor. All resources would be maintained in the absence of V CC . A power-down reset
is not issued since the low-power mode of most CMOS processors (Stop) is terminated with a Reset. A
pulsed interrupt ( NMI ) is issued to allow the CMOS processor to invoke a sleep mode to save power. For
this case, a power-on reset is desirable to wake up and initialize the processor. The CMOS mode is
invoked by connecting RC to V CCO .
An NMOS processor consumes more power, and consequently may not be battery backed. In this case, it
is desirable to notify the processor of a power-fail, then keep it in reset during the loss of V CC . This avoids
intermittent or aberrant operation. On power-up, the processor will continue to be reset until V CC reaches
an operational level to provide an orderly start. The NMOS mode is invoked by connecting RC to ground.
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