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| 型号： | DS1236AS-5N |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 6/19页 |
| 文件大小： | 0K |
| 描述： | IC MICROMANAGER 5% IND 16-SOIC |
| 标准包装： | 45 |
| 系列： | MicroManager |
| 类型： | 备用电池电路 |
| 监视电压数目： | 1 |
| 输出： | 开路漏极，推挽式 |
| 复位： | 高有效/低有效 |
| 复位超时： | 最小为 25 ms |
| 电压 - 阀值： | 4.62V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 16-SOIC W |
| 包装： | 管件 |
DS1236
low at the time power-fail detection occurs, CEO is held in its present state until CEI is returned high, or
the period t CE expires. This delay of write protection until the current memory cycle is completed prevents
the corruption of data. If CEO is in an inactive state at the time of V CC fail detection, CEO will be
unconditionally disabled within t CF . During nominal supply conditions CEO will follow CEI with a
maximum propagation delay of 20 ns. Figure 7 shows a typical nonvolatile SRAM application.
FRESHNESS SEAL
In order to conserve battery capacity during storage and/or shipment of an end system, the DS1236
provides a freshness seal to electrically disconnect the battery. Figure 8 depicts the three pulses below
ground on the IN pin required to invoke the freshness seal. The freshness seal will be disconnected and
normal operation will begin when V CC is cycled and reapplied to a level above V BAT .
To prevent negative pulses associated with noise from setting the freshness mode in system applications,
a series diode and resistor can be used to shunt noise to ground. During manufacturing, the freshness seal
can still be set by holding TP2 at -3 volts while applying the 0 to –3 volts clock to TP1.
POWER SWITCHING
When larger operating currents are required in a battery backed system, the 5-volt supply and battery
supply switches internal to the DS1236 may not be large enough to support the required load through
V CCO with a reasonable voltage drop. For these applications, the PF and PF outputs are provided to gate
external power switching devices. As shown in Figure 9, power to the load is switched from V CC to
battery on power-down, and from battery to V CC on power-up. The DS1336 is designed to use the PF
output to switch between V BAT and V CC . It provides better leakage and switchover performance than
currently available discrete components. The transition threshold for PF and PF is set to the external
battery voltage V BAT , allowing a smooth transition between sources. The load applied to the PF pin from
the external switch will be supplied by the battery. Therefore, if a discrete switch is used, this load should
be taken into consideration when sizing the battery.
RESET CONTROL
As mentioned above, the DS1236 supports two modes of operation. The CMOS mode is used when the
system incorporates a CMOS microprocessor which is battery backed. The NMOS mode is used when a
non-battery backed processor is incorporated. The mode is selected by the RC (Reset Control) pin. The
level of this pin distinguishes timing and level control on RST, RST , and NMI outputs for volatile
processor operation versus nonvolatile battery backup or battery operated processor applications.
ST/INPUT TIMING Figure 2
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相关PDF资料 |
PDF描述 |
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| DS1236AS-10N | IC MICROMANAGER 10% IND 16-SOIC |
| ACM18DSEH-S243 | CONN EDGECARD 36POS .156 EYELET |
| DS1239S-5N | IC MICROMAN W/FRESH 5%IND 16SOIC |
| DS1236S-5N | IC MICROMANAGER 5% IND 16-SOIC |
| DS1238S-10 | IC MICROMAN W/FRESH 10% 16-SOIC |
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