2
Altera Corporation
APEX 20K Programmable Logic Device Family Data Sheet
Preliminary Information
...and More
Features
s
Designed for low-power operation
–
1.8-V and 2.5-V supply voltage (see
Table 2)–
MultiVoltTM I/O interface support to interface with 1.8-V, 2.5-V,
–
ESB offering programmable power-saving mode
s
Flexible clock management circuitry with phase-locked loop (PLL)
–
Built-in low-skew clock tree
–
Up to eight global clock signals
–
ClockLockTM feature reducing clock delay and skew
–
ClockBoostTM feature providing clock multiplication
–
ClockShiftTM programmable clock phase and delay shifting
s
Powerful I/O features
–
Compliant with peripheral component interconnect Special
Interest Group (PCI SIG) PCI Local Bus Specification,
Revision 2.2
for 3.3-V operation at 33 or 66 MHz and 32 or 64 bits
–
Bidirectional I/O performance (tCO + tSU) up to 243 MHz
–
Direct connection from I/O pins to local interconnect providing
fast tCO and tSU times for complex logic
–
MultiVolt I/O interface support to interface with 1.8-V, 2.5-V,
–
Programmable clamp to VCCIO
–
Individual tri-state output enable control for each pin
–
Programmable output slew-rate control to reduce switching
noise
–
Support for advanced I/O standards, including low-voltage
differential signaling (LVDS), stub-series terminated logic
(SSTL-3), and Gunning transceiver logic (GTL+)
–
Supports hot-socketing operation
–
Pull-up on I/O pins before and during configuration
Table 2. APEX 20K Supply Voltages
Feature
EP20K100
EP20K200
EP20K400
EP20K60E
EP20K100E
EP20K160E
EP20K200E
EP20K300E
EP20K400E
EP20K600E
EP20K1000E
EP20K1500E
Internal supply voltage (VCCINT)
2.5 V
1.8 V
MultiVolt I/O interface voltage
levels (VCCIO)
2.5 V, 3.3 V
1.8 V, 2.5 V, 3.3 V