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Altera Corporation
APEX 20K Programmable Logic Device Family Data Sheet
Preliminary Information
In addition, two PLLs include special circuitry to support T1/E1
conversion. The T1 telecommunications standard uses a 1.544-MHz clock,
and the E1 telecommunications standard uses a 2.048-MHz clock. These
two PLLs can convert a T1 clock to an E1 clock, or vice versa.
Clock Phase & Delay Adjustment
The APEX 20KE ClockShift feature allows the clock phase and delay to be
adjusted. The clock phase can be adjusted by 90 steps. The clock delay can
be adjusted to increase or decrease the clock delay by approximately 2 ns
with 0.5-ns resolution.
LVDS Support
Two PLLs are designed to support the LVDS interface. When using LVDS,
the I/O clock runs at a slower rate than the data transfer rate. Thus, PLLs
are used to multiply the I/O clock internally to capture the LVDS data.
For example, an I/O clock may run at 50 MHz to support
400 Mbits/second LVDS data transfer. In this example, the PLL multiplies
the incoming clock by 8 to support the high-speed data transfer. The
LVDS interface is supported by EP20K300E and larger devices.
The APEX 20KE ClockLock circuitry supports individual LOCK signals.
The LOCK signal drives high when the ClockLock circuit has locked onto
the input clock. Both signals are optional for each ClockLock circuit; when
not used, they are I/O pins.
ClockLock & ClockBoost Timing Parameters
For the ClockLock and ClockBoost circuitry to function properly, the
incoming clock must meet certain requirements. If these specifications are
not met, the circuitry may not lock onto the incoming clock, which
generates an erroneous clock within the device. The clock generated by
the ClockLock and ClockBoost circuitry must also meet certain
specifications. If the incoming clock meets these requirements during
configuration, the ClockLock and ClockBoost circuitry will lock onto the
clock during configuration. The circuit will be ready for use immediately
after configuration.
Figure 31 shows the incoming and generated clock
specifications.