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| 型号： | EVAL-AD7262EDZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 33/33页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL CONTROL AD7262 |
| 标准包装： | 1 |
| ADC 的数量： | 2 |
| 位数： | 12 |
| 采样率（每秒）： | 1M |
| 数据接口： | 串行 |
| 输入范围： | 5 Vpp |
| 在以下条件下的电源（标准）： | 120mW @ 1MSPS |
| 工作温度： | -40°C ~ 105°C |
| 已用 IC / 零件： | AD7262 |
| 已供物品： | 板，CD |
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AD7262
Rev. 0 | Page 8 of 32
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
AD7262
TOP VIEW
(Not to Scale)
1
2
3
4
5
6
7
8
9
10
11
12
13
15 16 17 18 19 20 21 22 23 24
25
COUTD
26
COUTC
27
VDRIVE
28
DGND
29
COUTB
30
COUTA
31
DOUTB
32
DOUTA
33
AVCC
34
SCLK
35
CS
36
CAL
37
G3
38
G2
39
G1
40
G0
41
AV
CC
42
AG
ND
43
44
45
C
B
–
46
C
B
+
47
C
A
–
48
C
A
+
14
CA_CBVCC
AVCC
VA–
VA+
AGND
AVCC
AGND
VB+
VB–
AVCC
CC_CDVCC
AGND
C
+
C
–
C
D
+
C
D
–
C
_C
D
_G
N
D
V
REF
B
AG
ND
AV
CC
PD
2
PD
1
PD
0/
D
IN
RE
F
S
E
L
C
A
_C
B
_G
ND
V
RE
F
A
0
76
06
-00
3
07
60
6-
00
4
AD7262
TOP VIEW
(Not to Scale)
COUTD
COUTC
VDRIVE
DGND
COUTB
COUTA
DOUTB
DOUTA
AVCC
SCLK
CAL
CS
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
1
2
3
4
5
6
7
8
9
10
11
12
35
36
34
33
32
31
30
29
28
27
26
25
PIN 1
INDICATOR
CA_CBVCC
AVCC
VA–
VA+
AGND
AVCC
AGND
VB+
VB–
AVCC
CC_CDVCC
AGND
G3
G2
G1
G0
AV
CC
AG
ND
C
B
–
C
B
+
C
A
–
C
A
+
C
A
_C
B
_G
ND
V
REF
A
C
+
C
–
C
D
+
C
D
–
C
_C
D
_G
ND
V
RE
F
B
AG
ND
AV
CC
PD
2
PD
1
PD
0/
D
IN
RE
F
S
E
L
NOTES
1. THE EXPOSED METAL PADDLE ON THE BOTTOM OF THE LFCSP PACKAGE MUST
BE SOLDERED TO PCB GROUND FOR PROPER HEAT DISSIPATION AND ALSO FOR
NOISE AND MECHANICAL STRENGTH BENEFITS.
Figure 3. 48-Lead LQFP Pin Configuration
Figure 4. 48-Lead LFCSP Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
Description
2, 7, 11, 20, 33, 41
AVCC
Analog Supply Voltage, 4.75 V to 5.25 V. This is the supply voltage for the analog circuitry on the
AD7262/AD7262-5. All AVCC pins can be tied together. This supply should be decoupled to AGND
with a 100 nF ceramic capacitor per supply and a 10 μF tantalum capacitor.
1
CA_CBVCC
Comparator Supply Voltage, 2.7 V to 5.25 V. This is the supply voltage for Comparator A and
Comparator B. This supply should be decoupled to CA_CB_GND. AVCC, CC_CDVCC, and CA_CBVCC can be
tied together.
12
CC_CDVCC
Comparator Supply Voltage, 2.7 V to 5.25 V. This is the supply voltage for Comparator C and
Comparator D. This supply should be decoupled to CC_CD_GND. AVCC, CC_CDVCC, and CA_CBVCC can be
tied together.
4, 3
VA+, VA
Analog Inputs of ADC A. True differential input pair.
9, 10
VB+, VB
Analog Inputs of ADC B. True differential input pair.
43, 18
VREFA, VREFB
Reference Input/Output. Decoupling capacitors are connected to these pins to decouple the
internal reference buffer for each respective ADC. Typically, 1 μF capacitors are required to decouple
the reference. Provided the output is buffered, the on-chip reference can be taken from these pins
and applied externally to the rest of a system.
34
SCLK
Serial Clock. Logic input. A serial clock input provides the SCLK for accessing the data from the
AD7262/AD7262-5. This clock is also used as the clock source for the conversion process. A
minimum of 31 clocks is required to perform the conversion and access the 12-bit result.
36
CAL
Logic Input. Initiates an internal offset calibration.
21
PD2
Logic Input. Places the AD7262/AD7262-5 in selected shutdown mode in conjunction with the PD1
and PD0 pins (see Table 7).
22
PD1
Logic Input. Places the AD7262/AD7262-5 in selected shutdown mode in conjunction with the PD2
and PD0 pins (see Table 7).
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相关代理商/技术参数 |
参数描述 |
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