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参数资料
| 型号： | EVAL-ADF4350EB1Z |
| 厂商： | Analog Devices Inc |
| 文件页数： | 10/32页 |
| 文件大小： | 0K |
| 描述： | EVALUATION BOARD 1 FOR ADF4350 |
| 设计资源： | Broadband Low EVM Direct Conversion Transmitter Using LO Divide-by-2 Modulator (CN0144) |
| 标准包装： | 1 |
| 主要目的： | 计时，频率合成器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | ADF4350 |
| 主要属性： | 带 VCO 的单路分数-N 和整数-N PLL |
| 次要属性： | USB 接口 |
| 已供物品： | 板，缆线，CD |
| 其它名称： | Q4437453 Q4841122 Q5095480 Q5242312 Q5416250 |
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ADF4350
Rev. A | Page 18 of 32
REGISTER 0
Control Bits
With Bits [C3:C1] set to 0, 0, 0, Register 0 is programmed.
Figure 24 shows the input data format for programming this
register.
16-Bit INT Value
These sixteen bits set the INT value, which determines the
integer part of the feedback division factor. It is used in
Equation 1 (see the INT, FRAC, MOD, and R Counter
Relationship section). All integer values from 23 to 65,535
are allowed for 4/5 prescaler. For 8/9 prescaler, the minimum
integer value is 75.
12-Bit FRAC Value
The 12 FRAC bits set the numerator of the fraction that is input
to the Σ-Δ modulator. This, along with INT, specifies the new
frequency channel that the synthesizer locks to, as shown in the
RF Synthesizer—A Worked Example section. FRAC values from
0 to MOD 1 cover channels over a frequency range equal to
the PFD reference frequency.
REGISTER 1
Control Bits
With Bits [C3:C1] set to 0, 0, 1, Register 1 is programmed.
Figure 25 shows the input data format for programming
this register.
Prescaler Value
The dual modulus prescaler (P/P + 1), along with the INT,
FRAC, and MOD counters, determines the overall division
ratio from the VCO output to the PFD input.
Operating at CML levels, the prescaler takes the clock from the
VCO output and divides it down for the counters. It is based on
a synchronous 4/5 core. When set to 4/5, the maximum RF
frequency allowed is 3 GHz. Therefore, when operating the
ADF4350 above 3 GHz, this must be set to 8/9. The prescaler
limits the INT value, where P is 4/5, NMIN is 23 and P is 8/9,
NMIN is 75.
In the ADF4350, PR1 in Register 1 sets the prescaler values.
12-Bit Phase Value
These bits control what is loaded as the phase word. The word
must be less than the MOD value programmed in Register 1.
The word is used to program the RF output phase from 0° to
360° with a resolution of 360°/MOD. See the Phase Resync
section for more information. In most applications, the phase
relationship between the RF signal and the reference is not
important. In such applications, the phase value can be used
to optimize the fractional and subfractional spur levels. See the
more information.
If neither the phase resync nor the spurious optimization
functions are being used, it is recommended the PHASE
word be set to 1.
12-Bit Interpolator MOD Value
This programmable register sets the fractional modulus. This
is the ratio of the PFD frequency to the channel step resolution
on the RF output. See the RF Synthesizer—A Worked Example
section for more information.
REGISTER 2
Control Bits
With Bits [C3:C1] set to 0, 1, 0, Register 2 is programmed.
Figure 26 shows the input data format for programming this
register.
Low Noise and Low Spur Modes
The noise modes on the ADF4350 are controlled by DB30 and
DB29 in Register 2 (see Figure 26). The noise modes allow the
user to optimize a design either for improved spurious perfor-
mance or for improved phase noise performance.
When the lowest spur setting is chosen, dither is enabled. This
randomizes the fractional quantization noise so it resembles
white noise rather than spurious noise. As a result, the part is
optimized for improved spurious performance. This operation
would normally be used when the PLL closed-loop bandwidth
is wide, for fast-locking applications. Wide loop bandwidth is
seen as a loop bandwidth greater than 1/10 of the RFOUT channel
step resolution (fRES). A wide loop filter does not attenuate the
spurs to the same level as a narrow loop bandwidth.
For best noise performance, use the lowest noise setting option.
As well as disabling the dither, this setting also ensures that the
charge pump is operating in an optimum region for noise
performance. This setting is extremely useful where a narrow
loop filter bandwidth is available. The synthesizer ensures
extremely low noise and the filter attenuates the spurs. The
typical performance characteristics give the user an idea of
the trade-off in a typical W-CDMA setup for the different
noise and spur settings.
MUXOUT
The on-chip multiplexer is controlled by Bits [DB28:DB26] (see
Reference Doubler
Setting DB25 to 0 feeds the REFIN signal directly to the 10–bit
R counter, disabling the doubler. Setting this bit to 1 multiplies
the REFIN frequency by a factor of 2 before feeding into the
10-bit R counter. When the doubler is disabled, the REFIN
falling edge is the active edge at the PFD input to the fractional
synthesizer. When the doubler is enabled, both the rising and
falling edges of REFIN become active edges at the PFD input.
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