参数资料
型号: FIN1215MTD
厂商: Fairchild Semiconductor
文件页数: 20/20页
文件大小: 0K
描述: SERIALIZER/DESERIALIZER 48-TSSOP
标准包装: 38
功能: 串行器/解串器
数据速率: 1.785Gbps
输入类型: LVTTL
输出类型: LVDS
输入数: 21
输出数: 3
电源电压: 3 V ~ 3.6 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 48-TFSOP(0.240",6.10mm 宽)
供应商设备封装: 48-TSSOP
包装: 管件
2003 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FIN1215 / FIN1216 / FIN1217 Rev. 1.0.3
9
FIN
1215
/
FIN
1216
/
FIN
1217
LVD
S
21-
B
it
Serializers
/
D
e
-S
erializers
Transmitter AC Electrical Characteristics (Continued)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
Transmitter Output Data Jitter (f=85 MHz, FIN1217 only)
(12)
tTPPB0
Transmitter Output Pulse Position of Bit 0
Figure 20
7
f
1
a
×
=
-0.2
0
0.2
ns
tTPPB1
Transmitter Output Pulse Position of Bit 1
a-0.2
a
a+0.2
ns
tTPPB2
Transmitter Output Pulse Position of Bit 2
2a-0.2
2a
2a+0.2
ns
tTPPB3
Transmitter Output Pulse Position of Bit 3
3a-0.2
3a
3a+0.2
ns
tTPPB4
Transmitter Output Pulse Position of Bit 4
4a-0.2
4a
4a+0.2
ns
tTPPB5
Transmitter Output Pulse Position of Bit 5
5a-0.2
5a
5a+0.2
ns
tTPPB6
Transmitter Output Pulse Position of Bit 6
6a-0.2
6a
6a+0.2
ns
tJCC
Transmitter Clock Out Jitter, Cycle-to cycle
Figure 23
f=40MHz
350
370
ps
f=65MHz
210
230
f=85MHz
FIN1217 only
110
150
tTPLLS
Transmitter Phase Lock Loop Set Time
(13)
Figure 15
(12)
10.0
ms
Notes:
11. Outputs of all transmitters stay in 3-STATE until power reaches 2V. Clock and data output begins to toggle
10ms after VCC reaches 3V and /PwrDn pin is above 1.5V.
12. This output data pulse position works for both transmitters with 21 TTL inputs, except the LVDS output bit
mapping difference (see Figure 19). Figure 20 shows the skew between the first data bit and clock output. A
two-bit cycle delay is guaranteed when the MSB is output from transmitter.
13. This jitter specification is based on the assumption that PLL has a reference clock with cycle-to-cycle input jitter
of less than 2ns.
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