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参数资料
| 型号： | IBM37RGB524CF17A |
| 元件分类： | 显示控制器 |
| 英文描述： | 1600 X 1280 PIXELS PALETTE-DAC DSPL CTLR, PQFP144 |
| 封装： | QFP-144 |
| 文件页数： | 29/72页 |
| 文件大小： | 509K |
| 代理商： | IBM37RGB524CF17A |
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March 17, 1995
29
IBM
RGB524
Miscellaneous Control 2
Index:
0x0071
Access:
Read/Write
Power on Value: 0x00
Bits 7 - 6
PCLK SEL - Pixel Clock Select. Spec-
ies the source of the internal pixel
clock.
00
LCLK input
01
Internal PLL output
10
REFCLK input
11
Reserved
Note: A selection of 00 (LCLK input)
for the pixel clock is required
and only valid when PORT SEL
= 0 (VGA data inputs), or 32
BPP is selected with a VRAM
width of 32.
Bit 5
INTL MODE - Interlace Mode. Con-
trols effect of BORDER/OE input on
cursor when this input is used as the
ODD/EVEN interlace control.
0
Non-interlaced. The BOR-
DER/OE input is ignored.
1
Interlaced. If the cursor is
turned on, the BORDER/OE
input will be used to select dis-
play of the odd or even cursor
rows.
This bit has no effect when
BRDR/INTL (bit 1) is set ‘0’ (BOR-
DER/OE used as BORDER input).
Bit 4
BLANK CNTL - Blanking Control
0
Normal operation.
1
DACs are blanked. No pixel
data is presented on the DACs,
but all other operations remain
normal, including the collection
of a signature if the MISR is
turned on.
Bit 3
RSVD - Reserved
Bit 2
COL RES - Color Resolution
0
6-bit
1
8-bit
With 6-bit color resolution only 6 bits
of microprocessor data are loaded
into the palettes. Microprocessor
data bits D[5:0] are written to/read
from palette bits [7:2]. Internally 00
is written to palette bits [1:0], and on
reads D[7:6] are forced to 00.
Also with 6-bit color resolution the
two low order bits presented from the
palettes to the DACs are controlled
by Palette Control bit 6BIT LIN.
With 8-bit color resolution all 8 bits
from/to the microprocessor are writ-
ten/read to the palette, and the 8 bits
presented to the DACs are unmodi-
ed. The 6BIT LIN bit has no effect.
Bit 1
BRDR/INTL - Border/Interlace. Con-
trols usage of BORDER/OE input.
0
BORDER/OE input used to
indicate “BORDER”. (Interlace
operation is not supported.)
1
BORDER/OE input used to
indicate “ODD/EVEN”. (Border
operation is not supported.)
Bit 0
PORT SEL - Port Select
0
VGA Data inputs.
1
VRAM pixel port inputs.
0
1
2
3
4
5
6
7
RES
PCLK
SEL
MODE
INTL BLANK
CNTL
RSVD
PORT
SEL
COL BRDR/
INTL
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