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参数资料
| 型号： | IBM37RGB524CF17A |
| 元件分类： | 显示控制器 |
| 英文描述： | 1600 X 1280 PIXELS PALETTE-DAC DSPL CTLR, PQFP144 |
| 封装： | QFP-144 |
| 文件页数： | 50/72页 |
| 文件大小： | 509K |
| 代理商： | IBM37RGB524CF17A |
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48
March 17, 1995
RGB524
IBM
MISR Red
Index:
0x0084
Access:
Read Only
Power on Value: Undened
Bits 7 - 0
Multiple Input Signature Register
Red
This register along with MISR GREEN and MISR
BLUE is used to accumulate a diagnostic signature on
the values presented to the DACs. The input to the Red
DAC is the parallel data input to this portion of the
MISR.
MISR Green
Index:
0x0086
Access:
Read Only
Power on Value: Undened
Bits 7 - 0
Multiple Input Signature Register
Green
This register along with MISR RED and MISR BLUE is
used to accumulate a diagnostic signature on the values
presented to the DACs. The input to the Green DAC is
the parallel data input to this portion of the MISR.
MISR Blue
Index:
0x0088
Access:
Read Only
Power on Value: Undened
Bits 7 - 0
Multiple Input Signature Register
Blue
This register along with MISR RED and MISR GREEN
is used to accumulate a diagnostic signature on the val-
ues presented to the DACs. The input to the Blue DAC
is the parallel data input to this portion of the MISR.
Note: The reset, accumulation, and hold function of the
MISR is controlled by the MISR CNTL bit of the
Miscellaneous Control 1 register, and the BLANK input.
See 8.0 “Diagnostic Support” on page 23 for more
information.
0
1
2
3
4
5
6
7
MISR Red
0
1
2
3
4
5
6
7
MISR Green
0
1
2
3
4
5
6
7
MISR Blue
PLL VCO Divider Input
Index:
0x008e
Access:
Read Only
Power on Value: 0x00
Bits 7 - 6
DF - Desired Frequency
Bits 5 - 0
VCO DIV COUNT - VCO Divide
Count
This register allows readback of the selected PLL VCO
divider input. It is one of these registers:
u
F0, F1, F2, F3, F4, F5, F6, F7, F8, F9, F10, F11,
F12, F13, F14, F15
u
M0, M1, M2, M3, M4, M5, M6, M7
as determined by the PLL Control 1 EXT/INT bits (2:0),
the inputs FS[3:0], and PLL Control 2 INT FS bits (3:0).
PLL Reference Divider Input
Index:
0x008f
Access:
Read Only
Power on Value: Undened
Bits 7 - 5
Reserved
Bits 4 - 0
REF DIV COUNT - Reference Divide
Count
This register allows readback of the input to the PLL
reference divider.
u
Fixed PLL Reference Divider
u
N0, N1, N2, N3, N4, N5, N6, N7
as determined by the PLL Control 1 EXT/INT bits (2:0),
the inputs FS[3:0], and PLL Control 2 INT FS bits (3:0).
0
1
2
3
4
5
6
7
VCO DIV COUNT
DF
0
1
2
3
4
5
6
7
REF DIV COUNT
Reserved
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