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参数资料
| 型号： | IBM37RGB524CF17A |
| 元件分类： | 显示控制器 |
| 英文描述： | 1600 X 1280 PIXELS PALETTE-DAC DSPL CTLR, PQFP144 |
| 封装： | QFP-144 |
| 文件页数： | 52/72页 |
| 文件大小： | 509K |
| 代理商： | IBM37RGB524CF17A |
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50
March 17, 1995
RGB524
IBM
11.0 Pin Descriptions
Table 10. Pin Descriptions
Signal
Typ
e
Pin(s)
Description
Clocks and Clock Controls
REFCLK
I
80
Reference Clock. A xed frequency of 2 MHz to 100 MHz applied to this pin
provides the reference clock for the programmable pixel and system clock
PLLs. When the Direct Programming method is used the REFCLK
frequency range is 4 MHz to 62 MHz on 2 MHz boundaries.
FS[1:0]
I
96,83
Frequency Select. These two inputs select one of four sets of registers
containing the programming values for the pixel PLL.
DDOTCLK
O
116
Divided Dot Clock. The output of the pixel PLL, divided by 1, 2, 4, 8 or 16.
The divide factor is under register control. In 24 BPP Packed pixel mode the
SCLK signal can be selected for this output instead of the divided pixel PLL
output, under register control.
This output can be 3-stated under register control.
SCLK
O
113
Serial Clock. A divided version of the pixel PLL, where the divide ratio is
determined by the required bandwidth of the incoming pixels. When the PIX
port is selected, the SCLK frequency is a function of the VRAM width and
the pixel format (bits per pixel). SCLK is equal to the pixel PLL output when
the VGA port is selected.
This output can be 3-stated under register control.
LCLK
I
109
Load Clock. Latches data from the PIX port, the VGA port, and the video
control inputs.
SYSCLK
O
75
System Clock. The output of the SYSCLK programmable PLL. Also the
REFCLK input can be steered to this output.
This output can be 3-stated under register control.
Video Data Inputs
PIX[63:0]
I
10,9,8,7,67,66,65,64,
123,122,121,120.119,118,
117,140,139,138,137,136,
135,134,133,74,71,70,69,
68,6,5,4,3,2,1,144,143,
131,130,129,128,127,126,
125,124,56,55,54,53,52,
50,63,48,47,62,46,61,60,
59,58,45,44,57,49,43
Pixel data in from VRAMs.
Pixel data in can be selected as 64 or 32 bits using the VRAM SIZE bit of the
Miscellaneous Control 1 register. For 32 bit use inputs PIX[63:32] are not
used.
Latched on rising edge of LCLK.
VGA[7:0]
I
42,41,40,39,38,37,36,35
VGA data in. Latched on rising edge of LCLK.
Type: I = Input, O = Output, B = Bidirectional, C = Component
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