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参数资料
| 型号： | IBM37RGB524CF17A |
| 元件分类： | 显示控制器 |
| 英文描述： | 1600 X 1280 PIXELS PALETTE-DAC DSPL CTLR, PQFP144 |
| 封装： | QFP-144 |
| 文件页数： | 71/72页 |
| 文件大小： | 509K |
| 代理商： | IBM37RGB524CF17A |
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2
March 17, 1995
RGB524
IBM
1.1.3
Palette Read
Palette reads must be initialized by writing the Palette
Address (Read Mode) register. This provides a starting
address for reads and initializes the internal circuitry
for palette read operations.
Immediately following the writing of Palette Address
(Read Mode), a read of the palette will be performed at
the address just written. Internal palette data registers
are loaded with the read data, and the Palette Address
register is incremented.
Palette reads are then performed by reading from Pal-
ette Data. Red, green, blue... data from the preloaded
internal registers will be presented in sequence. Imme-
diately following every third read, an internal read of
the palette to the 24 bits contained in the internal regis-
ters will be performed at the address contained in the
Palette Address register.
Immediately following the internal palette read trig-
gered by the third read of Palette Data, the Palette
Address register will be incremented. Thus, continuous
reads of Palette Data will read the palette, stepping
through the palette addresses in ascending order.
1.1.4
6/8 Bit Palette Access
The original VGA had 6-bit DACs and 6-bit palette
entries, and the low order 6 bits from/to the microproces-
sor port were written/read into the palette.
For RGB524, the DACs and palette entries are 8 bits.
For non-VGA emulation all 8 bits are used. To emulate
6-bit VGA operation the upper 6 bits of the palette hold
the VGA 6-bit color and the two low order bits are set to
00. The COL RES bit (color resolution) of the Miscella-
neous Control 2 register determines if the access is 6-bit
or 8-bit.
The reset condition is to emulate VGA using the 6 low
order microprocessor data bits. COL RES is set to 6 bits.
In this mode, for writing, microprocessor bits [7:6] are
discarded, bits [5:0] are shifted to bits [7:2], and bits
[1:0] are set to 00 before being written into the internal
data registers. For reading, the internal data register
bits [7:2] are shifted to bits [5:0], and bits [7:6] are set to
00 before being presented on the microprocessor data
signals.
If COL RES is set to 8 bits then all 8 bits from/to the
microprocessor will be written to and read from the color
palette registers.
Note that the 6-to-8 bit translation is only done between
the microprocessor port and the internal data registers.
Internally, on writes, all 8 bits of the internal registers
are written to the palette, and on reads, the internal reg-
isters retain all 8 bits read from the palette. Thus, if the
palette is loaded with 8-bit values with COL RES set to
8 bits, and then the palette is read with COL RES set to
6 bits, the internal palette color registers will still be
loaded with the 8 bits that were written into the palette.
But the data read on the microprocessor data lines will
be 6 bits.
1.1.5
Palette Clocking
Palette accesses are synchronized internally with the
pixel clock. On writes, the pixel values of the previous
cycle are held and displayed during the write cycle. Both
of these features minimize disturbance of displayed pix-
els when the palette is accessed (anti-sparkle).
The pixel clock (as selected by the PCLK SEL bits in
Miscellaneous Control 2) must be running for palette
access to be valid.
The timings for the microprocessor signals are specied
in units of pixel clocks. These specications are derived
from the requirement for the pixel clock to be running
for palette access, as well as to allow time for the Palette
Accesses and Palette Address increments to occur inter-
nally following a palette access.
1.1.6
Palette Access Status
The original VGA logic had an override for read accesses
of the Palette Address (Read Mode) register. Instead of
reading the Palette Address register, a value was
returned that indicates the status of the last palette
access, write or read.
The reset condition of RGB524 is to return the address
value for a read of Palette Address (Read Mode). The
VGA logic may be emulated by setting the RADR RFMT
bit in Miscellaneous Control 1. This causes the status of
the last palette access to be returned.
The value of the status returned is 0x00 if the last write
to Palette Address was Write Mode, and 0x03 if the last
write to Palette Address was Read Mode.
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