参数资料
型号: IDT70121S35J8
厂商: IDT, Integrated Device Technology Inc
文件页数: 5/15页
文件大小: 0K
描述: IC SRAM 18KBIT 35NS 52PLCC
标准包装: 400
格式 - 存储器: RAM
存储器类型: SRAM - 双端口,异步
存储容量: 18K(2K x 9)
速度: 35ns
接口: 并联
电源电压: 4.5 V ~ 5.5 V
工作温度: 0°C ~ 70°C
封装/外壳: 52-LCC(J 形引线)
供应商设备封装: 52-PLCC(19x19)
包装: 带卷 (TR)
其它名称: 70121S35J8
IDT70121/IDT70125
High-Speed 2K x 9 Dual-Port Static RAM with Busy & Interrupt
Data Retention Characteristics (L Version Only)
Industrial and Commercial Temperature Ranges
Symbol
V DR
Parameter
V CC for Data Retention
Test Condition
Min.
2.0
Typ. (1)
___
Max.
___
Unit
V
I CCDR
t CDR (3)
t R (3)
Data Retention Current
Chip Deselect to Data Retention Time
Operation Recovery Time
V CC = 2V, CE > V CC - 0.2V
V IN > V CC - 0.2V or V IN < 0.2
IND.
COM'L.
___
___
t RC (2)
100
100
___
4000
1500
___
μA
V
2654 tbl 07
NOTES:
1. V CC = 2V, T A = +25°C, and are not production tested.
2. t RC = Read Cycle Time.
3. This parameter is guaranteed but is not production tested.
Data Retention Waveform
DATA RETENTION MODE
Vcc
CE
4.5V
t CDR
V IH
V DR ≥ 2V
V DR
4.5V
t R
V IH
2654 drw 03
AC Test Conditions
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
3ns
1.5V
1.5V
Figures 1 and 2
2654 tbl 08
DATA OUT
BUSY
5V
1250 ?
DATA OUT
5V
1250 ?
INT
775 ?
30pF
775 ?
5pF*
2654 drw 04
Figure 1. AC Output Test Load
5
Figure 2. Output Test Load
(For t LZ , t HZ , t WZ , t OW )
*Including scope and jig.
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