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参数资料
| 型号： | IDT82V3002APV |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 通信及网络 |
| 英文描述： | WAN PLL WITH DUAL REFERENCE INPUTS |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PDSO56 |
| 封装： | SSOP-56 |
| 文件页数： | 13/28页 |
| 文件大小： | 390K |
| 代理商： | IDT82V3002APV |
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13
IDT82V3002A WAN PLL WITH DUAL REFERENCE INPUTS INDUSTRIAL TEMPERATURE RANGE
Figure - 5 TIE Control Circuit Diagram
The TIE Control Block will work under the control of the Step
Generation circuit when it is enabled manually or automatically (by the
TIE_en pin or TIE auto-enable logic generated by the State Control
Circuit).
The selected reference signal is compared with the feedback signal
(current output feedback from the Frequency Select Circuit) by the
Measure Circuit. The phase difference between the input reference and
the feedback signal is sent to the Storage Circuit for TIE correction. The
Trigger Circuit generates a virtual reference with the phase corrected to
the same position as the previous reference according to the value
stored in the Storage Circuit. With this TIE correction mechanism, the
reference is switched without generating a step change in phase.
Figure - 6
shows the phase transient that would result if a reference
switch is performed with the TIE Control Block enabled.
Figure - 6 Reference Switch with TIE Control Block Enabled
The phase difference in the Storage Circuit can be cleared by
applying a logic low pulse to the
TCLR
pin. The reset pulse should be at
least 300 ns.
When the IDT82V3002A primarily enters Holdover Mode for short
time periods and then turns back to Normal Mode, the TIE Control
Circuit should not be enabled. This will prevent undesired accumulated
phase change between the input and output.
If the TIE Control Block is disabled manually or automatically during
the reference switching, the phase of the output signal will align with that
of the new reference. The phase slope is limited to 5 ns per 125 μs.
Figure - 7
shows the phase transient resulting from a reference switch
with the TIE Control Block disabled.
Step Generation
TIE_en
Select
Circuit
Fref0
Fref1
IN_sel
Measure
Circuit
Storage
Circuit
Trigger
Circuit
Feedback
signal
TCLR
Fref
Virtual
Reference
Signal
Input Clock
Fref0
Time = 0.00 s
Time = 0.25 s
Time = 0.50 s
Time = 0.75 s
Time = 1.0 s
Time = 1.25 s
Time = 1.50 s
Time = 1.75 s
Output Clock
Fref1
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相关代理商/技术参数 |
参数描述 |
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| IDT82V3002APVG | 功能描述:IC PLL WAN T1/E1 DUAL REF 56SSOP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:- 标准包装:1,500 系列:- 类型:时钟缓冲器/驱动器 PLL:是 主要目的:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 电源电压:3.3V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-SSOP（0.209"，5.30mm 宽） 供应商设备封装:28-SSOP 包装:带卷 (TR) 其它名称:93786AFT |
| IDT82V3002APVG8 | 功能描述:IC PLL WAN T1/E1 DUAL REF 56SSOP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:- 标准包装:1,500 系列:- 类型:时钟缓冲器/驱动器 PLL:是 主要目的:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 电源电压:3.3V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-SSOP（0.209"，5.30mm 宽） 供应商设备封装:28-SSOP 包装:带卷 (TR) 其它名称:93786AFT |
| IDT82V3010 | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:T1/E1/OC3 TELECOM CLOCK GENERATOR WITH DUAL REFERENCE INPUTS |
| IDT82V3010PV | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:T1/E1/OC3 TELECOM CLOCK GENERATOR WITH DUAL REFERENCE INPUTS |
| IDT82V3010PVG | 功能描述:IC PLL WAN 51/E1/OC3 DUAL 56SSOP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:- 标准包装:1,500 系列:- 类型:时钟缓冲器/驱动器 PLL:是 主要目的:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 电源电压:3.3V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-SSOP（0.209"，5.30mm 宽） 供应商设备封装:28-SSOP 包装:带卷 (TR) 其它名称:93786AFT |
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