参数资料
型号: IR3510MTRPBF
厂商: International Rectifier
文件页数: 14/36页
文件大小: 0K
描述: IC XPHASE CONTROL 32-MLPQ
标准包装: 1
系列: XPhase™
应用: 处理器
安装类型: 表面贴装
封装/外壳: 32-VFQFN 裸露焊盘
供应商设备封装: 32-MLPQ(5x5)
包装: 标准包装
产品目录页面: 1383 (CN2011-ZH PDF)
其它名称: IR3510MTRPBFDKR
IR3510
There is no unused or redundant silicon with the XPhase
TM
architecture compared to others such as a 4 phase
controller that can be configured for 2, 3, or 4 phase operation. PCB Layout is easier since the 5 wire bus
eliminates the need for point?to?point wiring between the Control IC and each Phase. The critical gate drive and
current sense connections are short and local to the Phase ICs. This improves the PCB layout by lowering the
parasitic inductance of the gate drive circuits and reducing the noise of the current sense signal.
PWM Control Method
The PWM block diagram of the XPhase
TM
architecture is also shown in Figure 1. Average current mode control
with trailing edge modulation is used. Dual error amplifiers, outer loop voltage error amplifier and inner loop current
error amplifier, are used in the Control IC to control the PWM duty cycle. An external RC circuit connected to the
input voltage and ground is used to program the slope of the PWM ramp and to provide the feed?forward control at
each phase. The PWM ramp slope will change with the input voltage and automatically compensate for changes in
the input voltage. The input voltage can change due to variations in the silver box output voltage or due to drops in
the PCB related to changes in load current.
Frequency and Phase Timing Control
The oscillator is located in the Control IC and its frequency is programmable from 150 kHz to 1MHZ by an external
resistor. The output of the oscillator is a 50% duty cycle triangle waveform with peak and valley voltages of
approximately 4.8V and 0.9V. This signal is used to program both the switching frequency and phase timing of the
Phase ICs. The Phase IC is programmed by resistor divider RRAMP1 and RRAMP2 connected between the
VBIAS reference voltage and the Phase IC LGND pin. A comparator in the Phase ICs detects the crossing of the
oscillator waveform with the voltage generated by the resistor divider and triggers a clock pulse that starts the
PWM cycle. The peak and valley voltages track the VBIAS voltage reducing potential Phase IC timing errors.
Figure 4 shows the Phase timing for an 8 phase converter. Note that both slopes of the triangle waveform can be
used for synchronization by swapping the RAMP + and – pins.
50% RAMP
DUTY CYCLE
SLOPE = 80mV / % DC
VPEAK (5.0V)
VPHASE4&5 (4.5V)
SLOPE = 1.6mV / ns @ 200kHz
SLOPE = 8.0mV / ns @ 1MHz
VPHASE3&6 (3.5V)
VPHASE2&7 (2.5V)
VPHASE1&8 (1.5V)
VVALLEY (1.00V)
CLK1
CLK2
CLK3
CLK4
CLK5
CLK6
CLK7
CLK8
Figure 2 – 8 Phase Oscillator Waveforms
Page 14 of 36
IR Confidential
May 18, 2009
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