参数资料
型号: LC708728V
元件分类: DAC
英文描述: SERIAL INPUT LOADING, 24-BIT DAC, PDSO20
封装: MO-150AE, SSOP-20
文件页数: 13/31页
文件大小: 332K
代理商: LC708728V
No. 7236-20/31
LC708728V
Register address
Bits
Symbol
Default
Description
(A3, A2, A1, A0)
0000
[7:0]
LAT [7:0]
11111111 (0 dB)
Left channel attenuation data for the 0.5 dB step attenuator. See table 9.
DACL attenuation
8
UPDATEL
0
Left channel attenuator load control
0: Save DACL in an intermediate register. (The output does not change.)
1: Save DACL and update the attenuation in both channels.
0001
[7:0]
RAT [7:0]
11111111 (0 dB)
Right channel attenuation data for the 0.5 dB step attenuator. See table 9.
DACR attenuation
8
UPDATER
0
Right channel attenuator load control
0: Save DACL in an intermediate register. (The output does not change.)
1: Save DACL and update the attenuation in both channels.
0010
0
MUT
0
Soft muting control
D/A converter control
0: Muting off
1: Muting on
1
DEEMPH
0
Deemphasis control
0: Deemphasis off
1: Deemphasis on
2
PWDN
0
Low power mode control
0: Normal operation. The output is active.
1: Low power mode. The output is muted.
[5:3]
IW [2:0]
0
Audio data format selection. See table 14.
0011
0
I2S0
Audio data format selection. See table 14.
Interface control
1
LRP
0
LRCIN/DSP mode selection
0: LRCIN normal/DSP late mode
1: LRCIN inverted/DSP early mode
2
ATC
0
Attenuator control
0: Use the set attenuations for the left and right channels.
1: Use the left channel attenuation data for the right channel.
4
REV
0
Output phase inversion
5
BCP
0
BCKIN polarity
0: Normal
1: Inverted
8
IZD
0
IZD and auto-mute control
0: IZD function disabled
1: IZD function enabled
Table 7 Register Bit Allocations
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