参数资料
| 型号： | M1A3P1000-1FG256I |
| 厂商： | Microsemi SoC |
| 文件页数： | 11/12页 |
| 文件大小： | 0K |
| 描述： | IC FPGA M1 1KB FLASH 1M 256FBGA |
| 标准包装： | 90 |
| 系列： | ProASIC3 |
| RAM 位总计： | 147456 |
| 输入/输出数： | 177 |
| 门数： | 1000000 |
| 电源电压： | 1.425 V ~ 1.575 V |
| 安装类型： | 表面贴装 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 256-LBGA |
| 供应商设备封装： | 256-FPBGA（17x17） |
ARM CortexTM-M1
8P ro d u c t B r i e f
Exception Priority
In the processor exception model, priority determines
when and how the processor takes exceptions. You can
assign software priority levels to interrupts.
The NVIC supports software-assigned priority levels. You
can assign a priority level from 0 to 3 to an interrupt by
writing to the 2-bit IP_N field in an Interrupt Priority
Register. Hardware priority decreases with increasing
interrupt number. Priority level –3 is the highest priority
level, and priority level 3 is the lowest. The priority level
overrides the hardware priority.
Stacks
The processor supports two separate stacks:
Process stack – You can configure Thread mode
to use the process stack. Thread mode uses the
main stack out of reset. SP_process is the Stack
Pointer (SP) register for the process stack.
Main stack – Handler mode uses the main stack.
SP_main is the SP register for the main stack.
Only one stack, the process stack or the main stack, is
visible at any time, using R13. After pushing the content,
the ISR uses the main stack, and all subsequent interrupt
preemptions use the main stack.
Clocking and Resets
The processor has one functional clock input, HCLK, and
one reset signal, SYSRESETn. If debug is implemented,
there is also a SWJ-DP clock, SWCLKTCK, and nTRST.
SWCLKTCK relates to the DAP logic. The debug reset
signal DBGRESETn relates to the debug logic clocked by
HCLK.
The SYSRESETn signal resets the entire processor system
with the exception of debug logic in the following:
Nested Vectored Interrupt Controller (NVIC)
Debug subsystem
The register file cannot be reset by SYSRESETn or
DBGRESETn.
Nested Vectored Interrupt Controller
The NVIC facilitates low-latency exception and interrupt
handling, and implements System Control Registers. The
NVIC supports reprioritizable interrupts. The NVIC and
the processor core interface are closely coupled, which
enables low latency interrupt processing and efficient
processing of late-arriving interrupts. All NVIC registers
are only accessible using word transfers. Any attempt to
write a halfword or byte individually causes corruption
of the register bits. All NVIC registers and system debug
registers are little-endian, regardless of the endianness
state of the processor. See Table 4 for a list of the NVIC
registers and their addresses
.
Table 4
NVIC Register
Name of Register
Type
Address
Reset Value
IRQ 0 to 31 Set Enable Register
R/W
0xE000E100
0x00000000
IRQ 0 to 31 Clear Enable Register
R/W
0xE000E180
0x00000000
IRQ 0 to 31 Set Pending Register
R/W
0xE000E200
0x00000000
IRQ 0 to 31 Clear Pending Register
R/W
0xE000E280
0x00000000
Priority 0 Register
R/W
0xE000E400
0x00000000
Priority 1 Register
R/W
0xe000e404
0x00000000
Priority 2 Register
R/W
0xe000e408
0x00000000
Priority 3 Register
R/W
0xe000e40c
0x00000000
Priority 4 Register
R/W
0xe000e410
0x00000000
Priority 5 Register
R/W
0xe000e414
0x00000000
Priority 6 Register
R/W
0xe000e418
0x00000000
Priority 7 Register
R/W
0xe000e41c
0x00000000
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