参数资料
| 型号： | X40411V8-BT1 |
| 厂商： | Intersil |
| 文件页数： | 13/24页 |
| 文件大小： | 0K |
| 描述： | IC VOLTAGE MON DUAL W/SUP 8TSSOP |
| 标准包装： | 2,500 |
| 类型： | 多压监控器 |
| 监视电压数目： | 2 |
| 输出： | 开路漏极或开路集电极 |
| 复位： | 高有效 |
| 复位超时： | 可调节/可选择 |
| 电压 - 阀值： | 2.6V，4.4V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 8-TSSOP |
| 包装： | 带卷 (TR) |
X40410, X40411, X40414, X40415
Figure 15. Random Address Read Sequence
Signals from
the Master
SDA Bus
Signals from
the Slave
S
t
a
r
t
Slave
Address
10 1
0 0
0
A
C
K
Byte
Address
A
C
K
S
t
a
r
t
Slave
Address
1
A
C
K
Data
S
t
o
p
– One bit of the slave command byte is a R/W bit. The
R/W bit of the Slave Address Byte defines the oper-
ation to be performed. When the R/W bit is a one,
then a read operation is selected. A zero selects a
write operation.
Word Address
The word address is either supplied by the master or
obtained from an internal counter. The internal counter
is undefined on a power-up condition.
Operational Notes
The device powers-up in the following state:
– The device is in the low power standby state.
– The WEL bit is set to ‘0’. In this state it is not possi-
ble to write to the device.
– SDA pin is the input mode.
– RESET/RESET Signal is active for t PURST .
Figure 16. Sequential Read Sequence
Data Protection
The following circuitry has been included to prevent
inadvertent writes:
– The WEL bit must be set to allow write operations.
– The proper clock count and bit sequence is required
prior to the stop bit in order to start a nonvolatile
write cycle.
– A three step sequence is required before writing into
the Control Register to change Watchdog Timer or
Block Lock settings.
Signals from
Slave
S
t
the Master
Address
A
C
K
A
C
K
A
C
K
o
p
SDA Bus
1
A
Signals from
the Slave
C
K
Data
(1)
Data
(2)
Data
(n-1)
Data
(n)
(n is any integer greater than 1)
13
FN8116.0
March 28, 2005
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