参数资料
型号: LTC1142LCG-ADJ
厂商: Linear Technology
文件页数: 14/20页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM CM 28-SSOP
标准包装: 47
PWM 型: 电流模式
输出数: 2
频率 - 最大: 250kHz
占空比: 100%
电源电压: 3.5 V ~ 18 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: 0°C ~ 70°C
封装/外壳: 28-SSOP(0.209",5.30mm 宽)
包装: 管件
LTC1142/LTC1142L/LTC1142HV
APPLICATIO S I FOR ATIO
Figure 5 shows how the efficiency losses in one section of
a typical LTC1142 regulator end up being apportioned.
The gate charge loss is responsible for the majority of the
and δ P = δ N = 0.007(63 – 25) = 0.27. The required R DS(ON)
for each MOSFET can now be calculated:
5 ( 2 ) ( 1 . 27 )
5 ( 2 ) ( 1 . 27 )
efficiency lost in the mid-current region. If Burst Mode
operation was not employed at low currents, the gate
charge loss alone would cause efficiency to drop to
unacceptable levels. With Burst Mode operation, the DC
supply current represents the lone (and unavoidable) loss
P - Ch R DS(ON) =
N - Ch R DS(ON) =
12 ( 0 . 25 )
2
12 ( 0 . 25 )
2
= 0 . 12 ?
= 0 . 085 ?
component which continues to become a higher percent-
age as output current is reduced. As expected, the I 2 R
losses dominate at high load currents.
Other losses including C IN and C OUT ESR dissipative
losses, MOSFET switching losses, Schottky conduction
losses during dead-time and inductor core losses, gener-
ally account for less than 2% total additional loss.
The P-channel requirement can be met by a Si9430DY,
while the N-channel requirement is exceeded by a
Si9410DY. Note that the most stringent requirement for
the N-channel MOSFET is with V OUT = 0 (i.e., short circuit).
During a continuous short circuit, the worst case
N-channel dissipation rises to:
P N = I SC(AVG)2 ? R DS(ON) ? (1 + δ N )
100
95
90
GATE CHARGE
1/2 LTC1142 I Q
I 2 R
With the 0.05 ? sense resistor, I SC(AVG) = 2A will result,
increasing the 0.085 ? N-channel dissipation to 450mW at
a die temperature of 73 ° C.
C IN will require an RMS current rating of at least 1A at
temperature, and C OUT will require an ESR of 0.05 ? for
optimum efficiency.
85
Now allow V IN to drop to its minimum value. At lower input
voltages the operating frequency will decrease and the
80
0.01
0.03
0.1 0.3
OUTPUT CURRENT (A)
1
3
P-channel will be conducting most of the time, causing its
power dissipation to increase. At V IN(MIN) = 7V:
Figure 5. Efficiency Loss
1142 F05
f MIN = (1/2.92 μ s)[1 – (5V/ 7V)] = 98kHz
5 V ( 0 . 12 ? )( 2 A ) ( 1 . 27 )
Design Example
As a design example, assume V IN = 12V (nominal), 5V
section, I MAX = 2A and f = 200kHz; R SENSE , C T and L can
immediately be calculated:
R SENSE = 100mV/2 = 0.05 ?
t OFF = (1/200kHz) ? [1 – (5/12)] = 2.92 μ s
C T5 = 2.92 μ s/(1.3 ? 10 4 ) = 220pF
L2 MIN = 5.1 ? 10 5 ? 0.05 ? ? 220pF ? 5V = 28 μ H
Assume that the MOSFET dissipations are to be limited to
P N = P P = 250mW.
2
P P = = 435 mV
7 V
A similar calculation for the 3.3V section results in the
component values shown in Figure 14.
LTC1142HV-ADJ/LTC1142L-ADJ
Adjustable Applications
When an output voltage other than 3.3V or 5V is required,
the LTC1142 adjustable version is used with an external
resistive divider from V OUT to V FB , Pin 2 (16). The regu-
lated output voltage is determined by:
V OUT = 1 . 25 ? 1 +
R 1 ?
If T A = 50°C and the thermal resistance of each MOSFET
is 50 ° C/ W, then the junction temperatures will be 63 ° C
14
?
?
R 2 ?
?
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