参数资料
型号: LTC1502IS8-3.3#TR
厂商: Linear Technology
文件页数: 6/8页
文件大小: 0K
描述: IC REG SWITCHED CAP 3.3V 8SOIC
标准包装: 2,500
类型: 切换式电容器(充电泵)
输出类型: 固定
输出数: 1
输出电压: 3.3V
输入电压: 0.9 V ~ 1.8 V
频率 - 开关: 500kHz
电流 - 输出: 10mA
同步整流器:
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
包装: 带卷 (TR)
供应商设备封装: 8-SOIC
LTC1502-3.3
APPLICATIO N S I N FOR M ATIO N
1
2
C2
C1 +
V OUT
C3 +
8
7
Output Ripple
Normal LTC1502-3.3 operation produces voltage ripple
100 ?
3
4
LTC1502-3.3
C1 – /SHDN C3 –
GND V IN
6
5
10 μ F
on the V OUT pin. Output voltage ripple is required for
regulation. Low frequency ripple exists due to the hyster-
esis in the sense comparator and propagation
ON OFF V CTRL
1502-3.3 F01
Figure 1. Pull-Down Circuitry for Shutdown
will force a logic high on the C1 – /SHDN pin and put the part
back into active mode. If no external pull-down is present
during the Hi-Z interval, the internal pull-up current will
maintain a logic high on the C1 – /SHDN pin thereby keep-
ing the part in active mode.
The shutdown feature can be used to prevent charge pump
switching during noise sensitive intervals. Since the charge
pump oscillator is disabled during shutdown, output switch-
ing noise can be eliminated while the external pull-down is
active. The LTC1502-3.3 takes between 20 μ s and 50 μ s to
switch from shutdown to active mode once the pull-down
device has been turned off (assuming a 100pF external
capacitance to GND on the C1 – /SHDN pin). A 100k pull-up
resistor from V IN to C1 – /SHDN will speed up this transition
by a factor of five at the expense of 10 μ A or so of additional
shutdown current. To maintain regulation, a sufficiently
large output capacitor must be used to prevent excessive
V OUT droop while the charge pump is in shutdown. Also,
there must be adequate time for the charge pump to
recharge the output capacitor while the part is active. In
other words, the average load current must be low enough
for the LTC1502-3.3 to maintain a 3.3V output while the
part is active.
delays in the charge pump enable/disable circuits. High
frequency ripple is also present mainly from the ESR
(equivalent series resistance) in the output capacitor. Typi-
cal output ripple (V IN = 1.25V) under maximum load is
50mV peak-to-peak with a low ESR 10 μ F output capacitor.
The magnitude of the ripple voltage depends on several
factors. High input voltages increase the output ripple
since more charge is delivered to C OUT per charging cycle.
Large output current load and/or a small output capacitor
(<10 μ F) results in higher ripple due to higher output
voltage dV/dt. High ESR capacitors (ESR > 0.5 ? ) on the
output pin cause high frequency voltage spikes on V OUT
with every clock cycle.
There are several ways to reduce the output voltage ripple.
A larger C OUT capacitor (22 μ F or greater) will reduce both
the low and high frequency ripple due to the lower C OUT
charging and discharging dV/dt and the lower ESR typi-
cally found with higher value (larger case size) capacitors.
A low ESR ceramic output capacitor will minimize the high
frequency ripple, but will not reduce the low frequency
ripple unless a high capacitance value is chosen. A reason-
able compromise is to use a 10 μ F to 22 μ F tantalum
capacitor in parallel with a 1 μ F to 3.3 μ F ceramic capacitor
on V OUT to reduce both the low and high frequency ripple.
An RC filter may also be used to reduce high frequency
voltage spikes (see Figure 2).
Capacitor Selection
For best performance, it is recommended that low ESR
V OUT
LTC1502-3.3
8
+
10 μ F
TANTALUM
1 μ F
CERAMIC
V OUT
2 ?
+
+
capacitors be used for C IN , C2 and C OUT to reduce noise
and ripple. The C IN , C2 and C OUT capacitors should be
either ceramic or tantalum and should be 10 μ F or greater.
If the input source impedance is very low (< 0.5 ? ), C IN
may not be needed. Ceramic capacitors are recommended
for the flying capacitors C1 and C3 with values of 0.47 μ F
to 2.2 μ F. Smaller values may be used in low output current
applications (e.g., I OUT < 1mA).
6
8
V OUT V OUT
LTC1502-3.3 10 μ F 10 μ F
1502-3.3 F02
Figure 2. Output Ripple Reduction Techniques
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