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参数资料
| 型号： | LTC2411CMS |
| 英文描述： | Analog-to-Digital Converter， 24-Bit |
| 中文描述： | 模拟到数字转换器，24比特 |
| 文件页数： | 16/40页 |
| 文件大小： | 450K |
| 代理商： | LTC2411CMS |
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LTC2411
23
Thus, for settling errors of less than 1ppm, the driving
source impedance should be chosen such that
τ≤13s/14
= 920ns. When an external oscillator of frequency fEOSC is
used, the sampling period is 2/fEOSC and, for a settling
error of less than 1ppm,
τ ≤ 0.14/fEOSC.
Input Current
If complete settling occurs on the input, conversion re-
sults will be unaffected by the dynamic input current. An
incomplete settling of the input signal sampling process
may result in gain and offset errors, but it will not degrade
the INL performance of the converter. Figure 11 shows the
mathematical expressions for the average bias currents
flowing through the IN+ and IN– pins as a result of the
sampling charge transfers when integrated over a sub-
stantial time period (longer than 64 internal clock cycles).
The effect of this input dynamic current can be analyzed
using the test circuit of Figure 12. The CPAR capacitor
includes the LTC2411 pin capacitance (5pF typical) plus
the capacitance of the test fixture used to obtain the results
shown in Figures 13 and 14. A careful implementation can
bring the total input capacitance (CIN + CPAR) closer to 5pF
thus achieving better performance than the one predicted
by Figures 13 and 14. For simplicity, two distinct situa-
tions can be considered.
For relatively small values of input capacitance (CIN <
0.01
F), the voltage on the sampling capacitor settles
almost completely and relatively large values for the
source impedance result in only small errors. Such values
for CIN will deteriorate the converter offset and gain
performance without significant benefits of signal filter-
ing and the user is advised to avoid them. Nevertheless,
when small values of CIN are unavoidably present as
parasitics of input multiplexers, wires, connectors or
sensors, the LTC2411 can maintain its exceptional accu-
racy while operating with relative large values of source
resistance as shown in Figures 13 and 14. These mea-
sured results may be slightly different from the first order
approximation suggested earlier because they include the
effect of the actual second order input network together
with the nonlinear settling process of the input amplifiers.
For small CIN values, the settling on IN+ and IN– occurs
almost independently and there is little benefit in trying to
match the source impedance for the two pins.
APPLICATIO S I FOR ATIO
WU
UU
CIN
2411 F12
VINCM + 0.5VIN
RSOURCE
IN+
LTC2411
CPAR
20pF
CIN
VINCM – 0.5VIN
RSOURCE
IN –
CPAR
20pF
RSOURCE ()
1
10
100
1k
10k
100k
+FS
ERROR
(ppm
OF
V
REF
)
2411 F13
50
40
30
20
10
0
VCC = 5V
REF+ = 5V
REF– = GND
IN+ = 5V
IN– = 2.5V
FO = GND
TA = 25°C
CIN = 0.01F
CIN = 0pF
CIN = 0.001F
CIN = 100pF
RSOURCE ()
1
10
100
1k
10k
100k
–
FS
ERROR
(ppm
OF
V
REF
)
2411 F14
0
–10
–20
–30
–40
–50
VCC = 5V
REF+ = 5V
REF – = GND
IN+ = GND
IN– = 2.5V
FO = GND
TA = 25°C
CIN = 0pF
CIN = 0.001F
CIN = 100pF
CIN = 0.01F
Figure 12. An RC Network at IN+ and IN–
Figure 13. +FS Error vs RSOURCE at IN+ or IN– (Small CIN)
Figure 14. –FS Error vs RSOURCE at IN+ or IN– (Small CIN)
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