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参数资料
| 型号： | LTC2411CMS |
| 英文描述： | Analog-to-Digital Converter， 24-Bit |
| 中文描述： | 模拟到数字转换器，24比特 |
| 文件页数： | 18/40页 |
| 文件大小： | 450K |
| 代理商： | LTC2411CMS |
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LTC2411
25
accuracy of the internal clock over the entire temperature
and power supply range is typical better than 1%. Such a
specification can also be easily achieved by an external
clock. When relatively stable resistors (50ppm/
°C) are
used for the external source impedance seen by IN+ and
IN–, the expected drift of the dynamic current, offset and
gain errors will be insignificant (about 1% of their respec-
tive values over the entire temperature and voltage range).
Even for the most stringent applications, a one-time
calibration operation may be sufficient.
In addition to the input sampling charge, the input ESD
protection diodes have a temperature dependent leakage
current. This current, nominally 1nA (
±10nA max), results
in a small offset shift. A 100
source resistance will create
a 0.1
V typical and 1V maximum offset voltage.
Reference Current
In a similar fashion, the LTC2411 samples the differential
reference pins REF+ and REF– transfering small amount of
charge to and from the external driving circuits thus
producing a dynamic reference current. This current does
not change the converter offset, but it may degrade the
gain and INL performance. The effect of this current can be
analyzed in the same two distinct situations.
For relatively small values of the external reference capaci-
tors (CREF < 0.01F), the voltage on the sampling capacitor
settles almost completely and relatively large values for
the source impedance result in only small errors. Such
values for CREF will deteriorate the converter offset and
gain performance without significant benefits of reference
filtering and the user is advised to avoid them.
Larger values of reference capacitors (CREF > 0.01F) may
be required as reference filters in certain configurations.
Such capacitors will average the reference sampling charge
and the external source resistance will see a quasi con-
stant reference differential impedance. When FO = LOW
(internal oscillator and 60Hz notch), the typical differential
reference resistance is 3.9M
which will generate a gain
error of approximately 0.13ppm for each ohm of source
resistance driving REF+ or REF–. When FO = HIGH (internal
oscillator and 50Hz notch), the typical differential refer-
ence resistance is 4.68M
whichwillgenerateagainerror
of approximately 0.11ppm for each ohm of source resis-
tance driving REF+ or REF–. When FO is driven by an
external oscillator with a frequency fEOSC (external conver-
sion clock operation), the typical differential reference
resistance is 0.60 1012/fEOSC and each ohm of source
resistance drving REF+ or REF– will result in
0.823 10–6 fEOSCppm gain error. The effect of the source
resistance on the two reference pins is additive with
respect to this gain error. The typical FS errors for various
combinations of source resistance seen by the REF+ and
REF– pins and external capacitance CREF connected to
these pins are shown in Figures 17 and 18. Typical – FS
errors are similar to + FS errors with opposite polarity.
APPLICATIO S I FOR ATIO
WU
UU
RSOURCE ()
1
10
100
1k
10k
100k
+FS
ERROR
(ppm
OF
V
REF
)
2411 F17a
0
–10
–20
–30
–40
–50
VCC = 5V
REF+ = 5V
REF – = GND
IN+ = 3.75V
IN – = 1.25V
FO = GND
TA = 25°C
CREF = 0.01F
CREF = 0.001F
CREF = 100pF
CREF = 0pF
Figure 17a. +FS Error vs RSOURCE at REF+ or REF– (Small CIN)
VINCM (V)
0
OFFSET
ERROR
(ppm
OF
V
REF
)
30
–30
40
–40
50
–50
4
2411 F16
20
–20
10
–10
0
1
C
D
F
0.5
2
1.5
3
3.5
4.5
2.5
5
FO = GND
TA = 25°C
RSOURCEIN– = 500
CIN = 10F
VCC = 5V
REF+ = 5V
REF – = GND
IN+ = IN– = VINCM
A:
RIN = +400
B:
RIN = +200
C:
RIN = +100
D:
RIN = 0
E:
RIN = –100
F:
RIN = –200
G:
RIN = –400
E
B
A
G
Figure 16. Offset Error vs Common Mode Voltage
(VINCM = IN
+ = IN–) and Input Source Resistance Imbalance
(
RIN = RSOURCEIN+ – RSOURCEIN–) for Large CIN Values (CIN ≥ 1F)
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