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参数资料
| 型号： | LTC3415EUHF#TRPBF |
| 厂商： | Linear Technology |
| 文件页数： | 22/28页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC ADJ 7A 38QFN |
| 标准包装： | 2,500 |
| 系列： | PolyPhase® |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 0.7 V ~ 5.5 V |
| 输入电压： | 2.5 V ~ 5.5 V |
| PWM 型： | 电流模式，混合 |
| 频率 - 开关： | 1.5MHz |
| 电流 - 输出： | 7A |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 38-WFQFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
| 供应商设备封装： | 38-QFN（5x7） |
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LTC3415
APPLICATIONS INFORMATION
Board Layout Considerations
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3415. Check the following in your layout:
1) Do the capacitors C IN connect to the power PV IN and
power PGND as closely as possible? These capacitors
provide the AC current to the internal power MOSFETs
and their drivers.
2) Are the C OUT and L1 closely connected? The (–) plate
of C OUT returns current to PGND and the (–) plate of
C IN .
3) The resistive divider, R1 and R2, must be connected
components. These copper areas should be connected to
one of the input supplies: PV IN , PGND, SV IN , or SGND.
Design Example
As a design example, consider using the LTC3415 in an
application with the following speci?cations:
V IN = 3.3V, V OUT = 1.8V, I OUT(MAX) = 7A,
I OUT(MIN) = 500mA, f = 1.5MHz
Because ef?ciency is important at both high and low load
current, Burst Mode operation or pulse-skipping operation
will be utilized. First calculate the inductor value for about
40% ripple current at maximum V IN :
between the (+) plate of C OUT and a ground line termi-
nated near SGND. The feedback signal V FB should be
L =
1.8V
1.5MHz ? 2.8A
1–
1.8V
3.3V
= 0.2 μ H
routed away from noisy components and traces, such
as the SW line, and its trace should be minimized.
4) Keep sensitive components away from the SW pin. The
input capacitor C IN , the compensation capacitor C C and
C ITH and all the resistors R1, R2, R C should be routed
away from the SW trace and the inductor L1.
C OUT will be selected based on the ESR that is required to
satisfy the output voltage ripple requirement and the bulk
capacitance needed for loop stability. For this design, two
100μF ceramic capacitors will be used.
C IN should be sized for a maximum current rating of:
5) A ground plane is preferred, but if not available, keep
the signal and power grounds segregated with small
signal components returning to the SGND pin at one
I RMS = 7A
2.5V
4.2V
4.2V
2.5V
– 1 = 3.43A
point which is then connected to the PGND pin.
Flood all unused areas on all layers with copper. Flooding
Decoupling the PV IN pins with three 47μF ceramic capaci-
tors is adequate for most applications.
with copper will reduce the temperature rise of power
3415fa
22
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