参数资料
型号: M24C16-WMB6
厂商: 意法半导体
元件分类: DRAM
英文描述: The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
中文描述: 该CAT24FC02是一个2 KB的EEPROM的国内256个8位每字举办的串行CMOS
文件页数: 16/25页
文件大小: 449K
代理商: M24C16-WMB6
M24C16, M24C08, M24C04, M24C02, M24C01
16/25
Table 13. AC Characteristics (M24Cxx-W)
Note: 1. For a reSTART condition, or following a Write cycle.
2. Sampled only, not 100% tested.
3. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.
4. Previous devices bearing the process letter “L” in the package marking guarantee a maximum write time of 10ms. For more infor-
mation about these devices and their device identification, please ask your ST Sales Office for Process Change Notices PCN MPG/
EE/0061 and 0062 (PCEE0061 and PCEE0062).
Table 14. AC Characteristics (M24Cxx-R)
Note: 1. For a reSTART condition, or following a Write cycle.
2. Sampled only, not 100% tested.
3. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.
4. This is preliminary information.
Test conditions specified in
Table 6.
and
Table 11.
Symbol
Alt.
Parameter
Min.
Max.
Unit
f
C
f
SCL
Clock Frequency
400
kHz
t
CHCL
t
HIGH
Clock Pulse Width High
600
ns
t
CLCH
t
LOW
Clock Pulse Width Low
1300
ns
t
DL1DL2 2
t
F
SDA Fall Time
20
300
ns
t
DXCX
t
SU:DAT
Data In Set Up Time
100
ns
t
CLDX
t
HD:DAT
Data In Hold Time
0
ns
t
CLQX
t
DH
Data Out Hold Time
200
ns
t
CLQV 3
t
AA
Clock Low to Next Data Valid (Access Time)
200
900
ns
t
CHDX 1
t
SU:STA
Start Condition Set Up Time
600
ns
t
DLCL
t
HD:STA
Start Condition Hold Time
600
ns
t
CHDH
t
SU:STO
Stop Condition Set Up Time
600
ns
t
DHDL
t
BUF
Time between Stop Condition and Next Start Condition
1300
ns
t
W 4
t
WR
Write Time
5
ms
Test conditions specified in
Table 7.
and
Table 10.
Symbol
Alt.
Parameter
Min.
4
Max.
4
Unit
f
C
f
SCL
Clock Frequency
400
kHz
t
CHCL
t
HIGH
Clock Pulse Width High
600
ns
t
CLCH
t
LOW
Clock Pulse Width Low
1300
ns
t
DL1DL2 2
t
F
SDA Fall Time
20
300
ns
t
DXCX
t
SU:DAT
Data In Set Up Time
100
ns
t
CLDX
t
HD:DAT
Data In Hold Time
0
ns
t
CLQX
t
DH
Data Out Hold Time
200
ns
t
CLQV 3
t
AA
Clock Low to Next Data Valid (Access Time)
200
900
ns
t
CHDX 1
t
SU:STA
Start Condition Set Up Time
600
ns
t
DLCL
t
HD:STA
Start Condition Hold Time
600
ns
t
CHDH
t
SU:STO
Stop Condition Set Up Time
600
ns
t
DHDL
t
BUF
Time between Stop Condition and Next Start Condition
1300
ns
t
W
t
WR
Write Time
10
ms
相关PDF资料
PDF描述
M24C16-WMB6G The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
M24C16-WMB6P The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
M24C16-WMB6T The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
M24C16-WMB6TG The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
M24C16-WMB6TP The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
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