8. Clock Generation Circuits
Figure 8.15
Procedure to Select PLL CLock for CPU Clock (Double-Speed Mode)
Start
NOTES:
1. Do not change values set in the MCD register while running in double-speed mode.
2. Do not generate any interrupts, DMA, and DMACII transfers during the indicated period.
3. Generate the waiting time for 2μs or more by executing the following program:
bset
7,
pm3
mov.b
#20,
R0L
WAIT_2μs:
dec.b
R0L
jne
WAIT_2μs
·
Set the PLC07 bit in the PLC0 register to 1
Set bits MCD4 to MCD0 in the MCD register(1)
Set the PM35 bit in the PM3 register to 1
Set the PM12 bit in the PM1 register to 1
Set the PM37 bit in the PM3 register
Waiting time is required for 2μs or more(3)
End
Set both bits PRC1 and PRC0
in the PRCR register to 1
Select from 00010b (divide by 2), 00100b (divide by 4),
01000b (divide by 8)
Set the CM17 bit in the CM1 register to 1
(note 2)
Program to generate the waiting time
Enable writing to registers associated with clocks
Set the CM21 bit in the CM2 register to 0
and the CM07 bit in the CM0 regsiter to 0
Select the main clock as the CPU clock source
(※Set after a main clock oscillation stabilizes)
Set registers PLC0 and PLC1
Select multiplication factor for the PLL clock
(※Set registers PLC0 and PLC1 simultaneously in 16-bit unit)
PLC1
PLC0
Multiplication factor for the PLL clock
00000010 01010100b
×4
00000010 01010110b
×6
00000010 01010000b
×8
PLL run
fPFC divide by 2
Select the PLL clock as the clock source for the CPU clock
and peripheral function clock
Set to 1 wait state
Set to double-speed mode
Disable writing to registers associated with clocks
Set both bits PRC1 and PRC0
in the PRCR register to 0
Wait for tsu(PLL)
Wait for PLL frequency synthesizer to stabilize