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参数资料
型号： M34584EDFP
元件分类： 微控制器/微处理器
英文描述： 4-BIT, OTPROM, 6 MHz, MICROCONTROLLER, PDSO42
封装： 0.450 INCH, 0.80 MM PITCH, PLASTIC, SSOP-42
文件页数： 14/159页
文件大小： 1166K
代理商： M34584EDFP
Skip condition
Number of
cycles
Number of
words
Instruction
code
D9
D0
Flag CY
2
16
Skip condition
Number of
cycles
Number of
words
Instruction
code
D9
D0
Flag CY
2
16
Skip condition
Number of
cycles
Number of
words
Instruction
code
D9
D0
Flag CY
2
16
Skip condition
Number of
cycles
Number of
words
Instruction
code
D9
D0
Flag CY
2
16
Rev.3.00
2004.08.06
page 108 of 155
REJ03B0010-0300Z
4584 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
TABP p (Transfer data to Accumulator and register B from Program memory in page p)
0010p5
p4
p3
p2
p1
p0
0p
13
–
Grouping:
Arithmetic operation
Operation:
(SP)
← (SP) + 1
(SK(SP))
← (PC)
(PCH)
← p
(PCL)
← (DR2–DR0, A3–A0)
(DR2)
← 0
(DR1, DR0)
← (ROM(PC))9, 8
(B)
← (ROM(PC))7–4
(A)
← (ROM(PC))3–0
(PC)
← (SK(SP))
(SP)
← (SP) – 1
8
+p
Description: Transfers bits 9 and 8 to register D, bits 7 to 4
to register B and bits 3 to 0 to register A.
These bits 7 to 0 are the ROM pattern in ad-
dress (DR2 DR1 DR0 A3 A2 A1 A0)2 specified
by registers A and D in page p.
The pages which can be referred as follows;
after the SBK instruction: 64 to 127
after the RBK instruction: 0 to 63
after system is released from reset or re-
turned from RAM back-up: 0 to 63.
TABE (Transfer data to Accumulator and register B from register E)
0000101010
02A
11
–
Grouping:
Register to register transfer
Description: Transfers the high-order 4 bits (E7–E4) of
register E to register B, and low-order 4 bits
of register E to register A.
Operation:
(B)
← (E7–E4)
(A)
← (E3–E0)
TABAD (Transfer data to Accumulator and register B from register AD)
1001111001
279
11
–
Grouping:
A/D conversion operation
Description: In the A/D conversion mode (Q13 = 0), trans-
fers the high-order 4 bits (AD9–AD6) of
register AD to register B, and the middle-or-
der 4 bits (AD5–AD2) of register AD to
register A. In the comparator mode (Q13 = 1),
transfers the middle-order 4 bits (AD7–AD4)
of register AD to register B, and the low-order
4 bits (AD3–AD0) of register AD to register A.
Operation:
In A/D conversion mode (Q13 = 0),
(B)
← (AD9–AD6)
(A)
← (AD5–AD2)
In comparator mode (Q13 = 1),
(B)
← (AD7–AD4)
(A)
← (AD3–AD0)
(Q13 : bit 3 of A/D control register Q1)
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
Note: p is 0 to 127 for
M34584MD/ED.
When this instruction
is executed, be careful
not to over the stack
because 1 stage of
stack register is used.
TABPS (Transfer data to Accumulator and register B from PreScaler)
1001110101
275
11
–
Grouping:
Timer operation
Description: Transfers the high-order 4 bits (TPS7–
TPS4) of prescaler to register B, and
transfers the low-order 4 bits (TPS3–TPS0)
of prescaler to register A.
Operation:
(B)
← (TPS7–TPS4)
(A)
← (TPS3–TPS0)
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