参数资料
型号: M38748EAF-XXXFS
厂商: Mitsubishi Electric Corporation
英文描述: SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述: 单芯片8位CMOS微机
文件页数: 24/92页
文件大小: 1292K
代理商: M38748EAF-XXXFS
24
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
INT
0
INT
1
Receive bus
interrupt source 1
Receive bus
interrupt source 2
Receive bus
interrupt source 3
Transmit bus
interrupt source 1
Transmit bus
interrupt source 2
Transmit bus
interrupt source 3
Timer X
Timer Y
Timer 2
Timer 3
INT
2
Serial I/O3
interrupt
CNTR
0
CNTR
1
Timer 1
INT
3
INT
4
INT
5
ADT
A-D converter
Serial I/O2
interrupt
Key input (key-
on wake-up)
Serial I/O1
receive
Serial I/O1
transmit
BRK instruction
Interrupt Request
Generating Conditions
Remarks
Interrupt Sources
Low
FFFC
16
FFFA
16
FFF8
16
FFF6
16
FFF4
16
FFF2
16
FFF0
16
FFEE
16
FFEC
16
FFEA
16
FFE8
16
FFE6
16
FFE4
16
FFE2
16
FFE0
16
FFDE
16
FFDC
16
High
FFFD
16
FFFB
16
FFF9
16
FFF7
16
FFF5
16
FFF3
16
FFF1
16
FFEF
16
FFED
16
FFEB
16
FFE9
16
FFE7
16
FFE5
16
FFE3
16
FFE1
16
FFDF
16
FFDD
16
Priority
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Table 7 Interrupt vector addresses and priority
Notes 1:
Vector addresses contain interrupt jump destination addresses.
2:
Reset function in the same way as an interrupt with the highest priority.
3:
Either ADT interrupt or A-D converter interrupt can be used. Both ADT interrupt and A-D converter interrupt cannot be used.
Vector Addresses
(Note 1)
Reset
(Note 2)
At reset
At detection of either rising or
falling edge of INT
0
input
At detection of either rising or
falling edge of INT
1
input
When receive bus interrupt
source 1 request bit becomes
“1” from “0”
When receive bus interrupt
source 2 request bit becomes
“1” from “0”
When receive bus interrupt
source 3 request bit becomes
“1” from “0”
When transmit bus interrupt
source 1 request bit becomes
“1” from “0”
When transmit bus interrupt
source 2 request bit becomes
“1” from “0”
When transmit bus interrupt
source 3 request bit becomes
“1” from “0”
At timer X underflow
At timer Y underflow
At timer 2 underflow
At timer 3 underflow
At detection of either rising or
falling edge of INT
2
input
At completion of serial I/O3 data
transmission/reception
At detection of either rising or
falling edge of CNTR
0
input
At detection of either rising or
falling edge of CNTR
1
input
At timer 1 underflow
At detection of either rising or
falling edge of INT
3
input
At detection of either rising or
falling edge of INT
4
input
At detection of either rising or
falling edge of INT
5
input
At falling of ADT pin input
Non-maskable
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
The condition which the receive
bus interrupt factor request bit
becomes “1” is defined according
to each communication protocol
specification confirmation.
The condition which the transmit
bus interrupt factor request bit
becomes “1” is defined according
to each communication protocol
specification confirmation.
External interrupt
(active edge selectable)
Valid only when serial I/O3 is
selected
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
Valid only when ADT interrupt is
selected
External interrupt
(falling valid)
Valid only when A-D converter
interrupt is selected
Valid only when serial I/O2 is
selected
External interrupt
(falling valid)
Valid only when serial I/O1 is
selected
Valid only when serial I/O1 is
selected
Non-maskable software interrupt
At completion of A-D converter
At completion of serial I/O2 data
transmission/reception
At falling of port P2
0
to P2
5
(at
input) input logical level AND
At completion of serial I/O1 data
reception
At completion of serial I/O1
transmission shift or when
transmission buffer is empty
At BRK instruction execution
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