- 您现在的位置：买卖IC网 > PDF目录365220 > M38748EAF-XXXFS (Mitsubishi Electric Corporation) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PDF资料下载
参数资料
| 型号： | M38748EAF-XXXFS |
| 厂商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 中文描述： | 单芯片8位CMOS微机 |
| 文件页数： | 65/92页 |
| 文件大小： | 1292K |
| 代理商： | M38748EAF-XXXFS |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页当前第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页
65
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
NOTES ON PROGRAMMING
Processor Status Register
The contents of the processor status register (PS) after a reset are
undefined, except for the interrupt disable flag (I) which is “1”. Af-
ter a reset, initialize flags which affect program execution. In
particular, it is essential to initialize the index X mode (T) and the
decimal mode (D) flags because of their effect on calculations.
Interrupts
The contents of the interrupt request bits do not change immedi-
ately after they have been written. After writing to an interrupt
request register, execute at least one instruction before performing
a BBC or BBS instruction.
Interrupt Source Determination
Use LDM, STA, etc., instructions to clear interrupt request bits
assigned to the interrupt source determination register 1, the in-
terrupt source determination register 2, the transmit status
register, or the receive status register. (Do not use read-modify-
write instructions such as CLB, SEB, etc. Use the LDM or STA
instruction to clear these bits.)
Request bits of interrupt source determination registers are not
automatically cleared when an interrupt occurs. After an inter-
rupt source has been determined, and before execution of the
RTI or CLI instruction, the user must clear the bit by program.
(Use the LDM or STA instruction to clear.)
The interrupt assigned to the interrupt source determination reg-
isters occur 1 instruction execution later than a normal interrupt.
The maximum timing is 16 machine cycles in the MUL, DIV in-
structions.
Decimal Calculations
To calculate in decimal notation, set the decimal mode flag (D)
to “1”, then execute an ADC or SBC instruction. After executing
an ADC or SBC instruction, execute at least one instruction be-
fore executing a SEC, CLC, or CLD instruction.
In decimal mode, the values of the negative (N), overflow (V),
and zero (Z) flags are invalid.
Timers
If a value n (between 0 and 255) is written to a timer latch, the fre-
quency division ratio is 1/(n+1).
Multiplication and Division Instructions
The index X mode (T) and the decimal mode (D) flags do not af-
fect the MUL and DIV instruction.
The execution of these instructions does not change the con-
tents of the processor status register.
Ports
The contents of the port direction registers cannot be read. The
following cannot be used:
The data transfer instruction (LDA, etc.)
The operation instruction when the index X mode flag (T) is “1”
The addressing mode which uses the value of a direction regis-
ter as an index
The bit-test instruction (BBC or BBS, etc.) to a direction register
The read-modify-write instructions (ROR, CLB, or SEB, etc.) to
a direction register.
Use instructions such as LDM and STA, etc., to set the port direc-
tion registers.
Serial I/O1
In clock synchronous serial I/O, if the receive side is using an
external clock and it is to output the S
RDY1
signal, set the trans-
mit enable bit, the receive enable bit, and the S
RDY
output
enable bit to “1”.
Serial I/O1 continues to output the final bit from the T
X
D pin af-
ter transmission is completed.
In order to stop a transmit, set the transmit enable bit to “0”
(transmit disable).
Do not set only the serial I/O1 enable bit to “0”.
A receive operation can be stopped by either setting the receive
enable bit to “0” or the serial I/O1 enable bit to “0”.
To stop a transmit when transferring in clock synchronous serial
I/O mode, set both the transmit enable bit and the receive en-
able bit to “0” at the same time.
To set the serial I/O1 control register again, first set the transmit
enable/receive enable bits to “0”. Next, reset the transmit/re-
ceive circuits, and, finally, reset the serial I/O1 control register.
Note when confirming the transmit shift register completion flag
and controlling the data transmit after writing a transmit data to
the transmit buffer. There is a delay of 0.5 to 1.5 shift clock
cycles while the transmit shift register completion flag goes from
“1” to “0”.
相关PDF资料 |
PDF描述 |
|---|---|
| M38748EAF-XXXGP | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M38748EDD-XXXFS | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M38748EDD-XXXGP | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M38748EDF-XXXFS | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M38748EDF-XXXGP | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
相关代理商/技术参数 |
参数描述 |
|---|---|
| M38748EAF-XXXGP | 制造商:MITSUBISHI 制造商全称:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M38748EAT-XXXFS | 制造商:MITSUBISHI 制造商全称:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M38748EAT-XXXGP | 制造商:MITSUBISHI 制造商全称:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M38748EBD-XXXFS | 制造商:MITSUBISHI 制造商全称:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M38748EBD-XXXGP | 制造商:MITSUBISHI 制造商全称:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
发布紧急采购，3分钟左右您将得到回复。