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参数资料
| 型号： | M38D59GF-XXXFP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, MROM, 6.25 MHz, MICROCONTROLLER, PQFP80 |
| 封装： | 14 X 20 MM, 0.80 MM PITCH, PLASTIC, QFP-80 |
| 文件页数： | 65/142页 |
| 文件大小： | 2004K |
| 代理商： | M38D59GF-XXXFP |
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Rev.3.04
May 20, 2008
REJ03B0158-0304
38D5 Group
Fig. 18 Interrupt control
Interrupt Disable Flag
The interrupt disable flag is assigned to bit 2 of the processor
status register. This flag controls the acceptance of all interrupt
requests except for the BRK instruction. When this flag is set to
“1”, the acceptance of interrupt requests is disabled. When it is
set to “0”, acceptance of interrupt requests is enabled. This flag is
set to “1” with the SEI instruction and set to “0” with the CLI
instruction.
When an interrupt request is accepted, the contents of the
processor status register are pushed onto the stack while the
interrupt disable flag remains set to “0”. Subsequently, this flag
is automatically set to “1” and multiple interrupts are disabled.
To use multiple interrupts, set this flag to “0” with the CLI
instruction within the interrupt processing routine.
The contents of the processor status register are popped off the
stack with the RTI instruction.
Interrupt Request Bits
Once an interrupt request is generated, the corresponding
interrupt request bit is set to “1” and remains “1” until the request
is accepted . Wh en the reques t is accepted, th is bit is
automatically set to “0”.
Each interrupt request bit can be set to “0”, but cannot be set to
“1”, by software.
Interrupt Enable Bits
The interrupt enable bits control the acceptance of the
corresponding interrupt requests. When an interrupt enable bit is
set to “0”, the acceptance of the corresponding interrupt request
is disabled. If an interrupt request occurs in this condition, the
corresponding interrupt request bit is set to “1”, but the interrupt
request is not accepted. When an interrupt enable bit is set to “1”,
acceptance of the corresponding interrupt request is enabled.
Each interrupt enable bit can be set to “0” or “1” by software.
The interrupt enable bit for an unused interrupt should be set to
“0”.
Interrupt Source Selection
Any of the following combinations can be selected by the
interrupt edge selection register (003A16).
Timer Y or CNTR1
External Interrupt Pin Selection
For external interrupts INT0 and INT1, the INT0, INT1 input port
switch bit in the interrupt edge selection register (bits 4 and 5 of
address 003A16) can be used to select INT00 and INT01 pin input
or INT10 and INT11 pin input.
Interrupt request bit
Interrupt enable bit
Interrupt disable flag (I)
BRK instruction
Reset
Interrupt
acceptance
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