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参数资料
| 型号： | M4A3-384/192-10AC |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | PLD |
| 英文描述： | High Performance E 2 CMOS In-System Programmable Logic |
| 中文描述： | EE PLD, 10 ns, PBGA256 |
| 封装： | BGA-256 |
| 文件页数： | 15/61页 |
| 文件大小： | 1072K |
| 代理商： | M4A3-384/192-10AC |
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ispMACH 4A Family
All ispMACH 4A devices have a programmable bit that congures all inputs and I/Os with either
pull-up or Bus-Friendly characteristics. If the device is congured in pull-up mode, all inputs
and I/O pins are weakly pulled up. For the circuit diagram, please refer to the document entitled
MACH Endurance Characteristics on the Lattice Data Book CD-ROM or Lattice web site.
POWER MANAGEMENT
Each individual PAL block in ispMACH 4A devices features a programmable low-power mode,
which results in power savings of up to 50%. The signal speed paths in the low-power PAL block
will be slower than those in the non-low-power PAL block. This feature allows speed critical
paths to run at maximum frequency while the rest of the signal paths operate in the low-power
mode.
PROGRAMMABLE SLEW RATE
Each ispMACH 4A device I/O has an individually programmable output slew rate control bit.
Each output can be individually congured for the higher speed transition (3 V/ns) or for the
lower noise transition (1 V/ns). For high-speed designs with long, unterminated traces, the slow-
slew rate will introduce fewer reections, less noise, and keep ground bounce to a minimum.
For designs with short traces or well terminated lines, the fast slew rate can be used to achieve
the highest speed. The slew rate is adjusted independent of power.
POWER-UP RESET/SET
All ip-ops power up to a known state for predictable system initialization. If a macrocell is
congured to SET on a signal from the control generator, then that macrocell will be SET during
device power-up. If a macrocell is congured to RESET on a signal from the control generator
or is not congured for set/reset, then that macrocell will RESET on power-up. To guarantee
initialization values, the VCC rise must be monotonic, and the clock must be inactive until the
reset delay time has elapsed.
SECURITY BIT
A programmable security bit is provided on the ispMACH 4A devices as a deterrent to
unauthorized copying of the array conguration patterns. Once programmed, this bit defeats
readback of the programmed pattern by a device programmer, securing proprietary designs from
competitors. Programming and verication are also defeated by the security bit. The bit can only
be reset by erasing the entire device.
HOT SOCKETING
ispMACH 4A devices are well-suited for those applications that require hot socketing capability.
Hot socketing a device requires that the device, when powered down, can tolerate active signals
on the I/Os and inputs without being damaged. Additionally, it requires that the effects of the
powered-down MACH devices be minimal on active signals.
相关PDF资料 |
PDF描述 |
|---|---|
| M4A3-384/192-10AI | High Performance E 2 CMOS In-System Programmable Logic |
| M4A3-384/192-14AI | High Performance E 2 CMOS In-System Programmable Logic |
| M4A3-384/192-65AC | High Performance E 2 CMOS In-System Programmable Logic |
| M4A3-256/128-12AI | High Performance E 2 CMOS In-System Programmable Logic |
| M4A3-256/128-55AC | High Performance E 2 CMOS In-System Programmable Logic |
相关代理商/技术参数 |
参数描述 |
|---|---|
| M4A3-512/160-10YC | 功能描述:CPLD - 复杂可编程逻辑器件 HI PERF E2CMOS PLD RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| M4A3-512/160-10YI | 功能描述:CPLD - 复杂可编程逻辑器件 HI PERF E2CMOS PLD RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| M4A3-512/160-12YC | 功能描述:CPLD - 复杂可编程逻辑器件 HI PERF E2CMOS PLD RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| M4A3-512/160-12YI | 功能描述:CPLD - 复杂可编程逻辑器件 HI PERF E2CMOS PLD RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| M4A3-512/160-14YI | 功能描述:CPLD - 复杂可编程逻辑器件 HI PERF E2CMOS PLD RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
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