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参数资料
| 型号： | M66004SP |
| 元件分类： | 显示控制器 |
| 英文描述： | 36 X 16 DOTS FLUORESCENT DSPL CTRL, PDIP64 |
| 封装： | PLASTIC, DIP-64 |
| 文件页数： | 12/15页 |
| 文件大小： | 3009K |
| 代理商： | M66004SP |
M66238FP
REJ03F0268-0200 Rev.2.00 Mar 18, 2008
Page 6 of 14
Register Configuration
1. Clock frequency setting command
Reference clock generation 12-bit division ratio, PLL synthesizer 15-bit division ratio and CKO/PLLO division ratio
are set at address (A1, A0) = (0, 0).
Data Bit
Description
Default
0
D0
1
0
D1
1
0
D2
1
0
D3
1
0
D4
1
0
D5
1
0
D6
1
0
D7
1
0
D8
1
0
D9
1
0
D10
1
0
D11
1
12-bit reference clock dividing ratio is set.
D11 and D0 correspond to MSB and LSB, respectively.
K =
Σ (Dk × 2k)
k = 0
11
K: Reference clock dividing ratio
0
D12
1
0
D13
1
0
D14
1
0
D15
1
0
D16
1
0
D17
1
0
D18
1
0
D19
1
0
D20
1
0
D21
1
0
D22
1
0
D23
1
0
D24
1
0
D25
1
0
D26
1
15-bit PLL synthesizer dividing ratio is set.
D26 and D12 correspond to MSB and LSB, respectively.
N =
Σ (Dn × 2n-12)
n = 12
26
N: PLL synthesizer dividing ratio
0
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相关代理商/技术参数 |
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