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参数资料
| 型号： | M88 |
| 厂商： | 意法半导体 |
| 英文描述： | In-System Programmable ISP Multiple-Memory and Logic FLASHPSD Systems with CPLD for MCUs |
| 中文描述： | 在系统可编程ISP的多内存和CPLD的逻辑FLASHPSD系统的微控制器 |
| 文件页数： | 1/7页 |
| 文件大小： | 67K |
| 代理商： | M88 |
1/7
DATA BRIEFING
June 2000
Complete data available on Data-on-Disc CD-ROM or at www.st.com
M88 FAMILY
In-System Programmable (ISP) Multiple-Memory and
Logic FLASH+PSD Systems (with CPLD) for MCUs
I
Single Supply Voltage:
– 5 V
±
10% for M88xxFxY
– 3 V (+20/–10%) for M88xxFxW
I
1 or2 Mbit of Primary Flash Memory (8 uniform
sectors, 16K x 8, or 32K x 8)
I
A second non-volatile memory:
– 256 Kbit (32K x 8) EEPROM (for M8813F1x)
or Flash memory (for M88x3F2x)
– 4 uniform sectors (8K x 8)
I
SRAM (16 Kbit, 2K x 8; or 64 Kbit, 8K x 8)
I
Over 3,000 Gates of PLD: DPLD and CPLD
I
27 Reconfigurable I/O ports
I
Enhanced JTAG Serial Port
I
Programmable power management
I
Stand-by current:
– 50
μ
A for M88xxFxY
– 25
μ
A for M88xxFxW
I
High Endurance:
– 100,000 Erase/Write Cycles of FlashMemory
– 10,000 Erase/Write Cycles of EEPROM
– 1,000 Erase/Write Cycles of PLD
DESCRIPTION
The FLASH+PSD family of memory systems for
microcontrollers
(MCUs)
brings
In-System-
Figure 1. Logic Diagram
AI02856
16
AD0-AD15
PC0-PC7
VCC
FLASH+PSD
VSS
8
PD0-PD2
3
PB0-PB7
8
PA0-PA7
8
3
CNTL0-
CNTL2
RESET
Table 1. Signal Names
PA0-PA7
Port-A
PB0-PB7
Port-B
PC0-PC7
Port-C
PC2 = Voltage Stand-by
PD0-PD2
Port-D
AD0-AD15
Address/Data
CNTL0-CNTL2
Control
RESET
Reset
V
CC
Supply Voltage
V
SS
Ground
PLCC52 (K)
PQFP52 (T)
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