参数资料
型号: MAX7349AWG
厂商: MAXIM INTEGRATED PRODUCTS INC
元件分类: 微控制器/微处理器
英文描述: SPECIALTY MICROPROCESSOR CIRCUIT, PDSO24
封装: 0.300 INCH, MS-013AD, SOIC-24
文件页数: 9/28页
文件大小: 760K
代理商: MAX7349AWG
MAX7347/MAX7348/MAX7349
2-Wire Interfaced Low-EMI Key Switch and
Sounder Controllers
______________________________________________________________________________________
17
REGISTER DATA
REGISTER
ADDRESS
CODE (hex)
D7
D6
D5
D4
D3
D2
D1
D0
INTERRUPT REGISTER
0x03
INT
STATUS*
ALERT
EVENT*
KEY-
SCAN
EVENT*
KEY-SCAN INTERRUPT
FREQUENCY
Current INT is due to key-scan event(s)
0x03
1
0
1
X
XX
X
Current INT is due to alert event
0x03
1
0
X
XX
X
Current INT is due to both key-scan event(s)
and alert event
0x03
1
X
XX
X
INT has not been asserted
0x03
0
X
XX
X
INT has been asserted
0x03
1
ALERT
EVENT
KEY-
SCAN
EVENT
X
XX
X
INT output pin is NOT asserted; INT output
pin is used as a general-purpose output
called INT port under control of bit D6 in
ports register; INT status bits D5, D6, D7 are
still set and cleared in the normal way at the
end of every debounce cycle as if bits D4–D0
were set to 00001
0x03
X
0
00
0
Key-scan INT is asserted at the end of every
debounce cycle, if new key(s) is debounced
0x03
X
0
00
0
1
Key-scan INT is asserted at the end of every
2 debounce cycles, if new key(s) is
debounced
0x03
X
0
00
1
0
-—
——
Key-scan INT is asserted at the end of every
29 debounce cycles, if new key(s) is
debounced
0x03
X
1
11
0
1
Key-scan INT is asserted at the end of every
30 debounce cycles, if new key(s) is
debounced
0x03
X
1
11
1
0
Key-scan INT is asserted at the end of every
31 debounce cycles, if new key(s) is
debounced
0x03
X
1
11
1
Power-up default setting
0x03
00
0
00
0
Table 11. Interrupt Register Format
*Read-only register bits; write data is ignored. Reading the interrupt register does clear an alert event INT, but does not clear a key-
scan event INT. INT caused by key-scan event(s) is cleared when FIFO is emptied.
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