313
13.3 Registers of the DMA Controller
Reset initializes these bits to 000.
Writing 000 clears these bits.
These bits can be read and written but 000 is the only write value valid for this bit.
Bit 23: ERIE (Error Interrupt Enable)
This bit controls the generation of an interrupt at abnormal termination.
DSS3 to DSS0
indicate the contents of an error. Note that only specific end resources cause this interrupt.
(See explanations of the DSS2 to DSS0 bits.)
0: Disable error interrupt request output (Initial value)
1: Enable error interrupt request output
Reset initializes this bit to 0.
This bit can be read and written.
Bit 22: EDIE (End Interrupt Enable)
This bit controls the generation of an interrupt at normal termination.
0: Disable end interrupt request output (Initial value)
1: Enable end interrupt request output
Reset initializes this bit to 0.
This bit can be read and written.
Bits 21 and 20: (Reserved)
The read value is not defined.
Bits 19 and 18: EPSE, EPDE (End of Processor Source/Dest-tim Enable)
These bits control pulse output to the transfer end output pins (DEQOP1 to DEOP2).
When the EPSE bit is 1, the DMA end signal is output at the source address access timing.
When the EPDE bit is 1, the DMA end signal is output at the destination address access
timing.
Reset initializes these bits to 00.
These bits can be read and written.
Bits 17 and 16: AKOE (Acknowledge Output Enable)
These bits control pulse output to the transfer request acknowledge pins (DACK0 to
DACK2).
When the AKSE bit is 1, the DMA end signal is output at the source address access timing.
When the AKDE bit is 1, the DMA end signal is output at the destination address access
Table 13.3-2 DMA Transfer End Signal Output Timings
EPSE
EPDE
Transfer end signal output timing
0
Disable signal output (Initial value)
0
1
Output at destination address access timing
1
0
Output at source address access timing
1
Output at source and destination address access timings