420
INDEX
Index
Numerics
0-detection ........................................................... 355
0-detection (BSD0), data register for.................... 353
16/32-bit immediate value transfer instruction,
immediate value set and ............................ 403
16-bit reload timer, block diagram of .................... 213
16-bit reload timer, feature of ............................... 212
16-bit reload timer, register of .............................. 214
16-bit timer register (TMR) ................................... 218
16-bit timer register (TMRLR)............................... 218
1-detection ........................................................... 355
1-detection (BSD1), data register for.................... 353
20-bit delayed branch macroinstruction ............... 411
20-bit ordinary branch macroinstruction ............... 409
32-bit delayed branch macroinstruction ............... 415
32-bit ordinary branch macroinstruction ............... 413
A
A/D converter operation mode ............................. 277
A/D converter, block diagram of ........................... 269
A/D converter, feature of ...................................... 268
A/D converter, other note on ................................ 281
A/D converter, register of ..................................... 270
AC characteristic of DMA controller ..................... 346
addition and subtraction instruction...................... 400
address register specification............................... 330
addressing mode symbol ..................................... 395
all-L or all-H PPG output method ......................... 237
another transfer request during transfer............... 345
area mask register (AMR), area selection register
(ASR) and ................................................. 119
area mode register 0 (AMD0)............................... 122
area mode register 1 (AMD1)............................... 124
area mode register 32 (AMD32)........................... 125
area mode register 4 (AMD4)............................... 126
area mode register 5 (AMD5)............................... 127
area selection register (ASR) and area mask register
(AMR)......................................................... 119
assembler source, sample ..................................... 97
asynchronous (step-synchronous) mode, transfer
data format in ............................................ 298
automatic wait cycle for CBR refresh ................... 194
automatic wait cycle timing................................... 172
automatic wait cycle timing of ordinary DRAM
interface ..................................................... 182
B
basic read cycle timing......................................... 163
basic write cycle timing ........................................ 165
big-endian bus access ......................................... 139
bit operation instruction........................................ 401
bit ordering ............................................................. 48
bit search module, block diagram of .................... 352
bit search module, register of............................... 352
block transfer ....................................................... 327
block using peripheral clock................................... 88
branch instruction with delay slot ........................... 54
branch instruction with delay slot, limitation on
operation of................................................. 55
branch instruction with delay slot, operation of ...... 54
branch instruction with no delay slot ...................... 57
branch instruction with no delay slot, operation of . 57
burst transfer........................................................ 326
bus interface register ........................................... 118
bus interface, block diagram of ............................ 117
bus interface, feature of ....................................... 114
bus privilege, release of ....................................... 195
bus width, combination of .................................... 130
byte access .......................................................... 154
byte ordering .......................................................... 48
C
cache entry update ................................................ 38
CAS before RAS (CBR) refresh........................... 193
CBR refresh, automatic wait cycle for.................. 194
change point detection......................................... 356
change point detection (BSDC), data register for 354
channel group ...................................................... 341
chip select area.................................................... 114
CLK synchronous mode, transfer data format in . 299
clock doubler function on/off, combination of
operating frequencies by ............................ 95
clock doubler function on/off, precaution on .......... 95
clock doubler function, activating ........................... 94
clock doubler function, deactivating ....................... 94
clock generator, block diagram of .......................... 74
clock generator, register of .................................... 74
clock system, reference drawing of........................ 97
column address, row address and ....................... 157