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CHAPTER 3 CPU
3.9
Outline of Instructions
The FR Series supports the general RISC instruction set and also a set of logical
operation instructions, bit operation instructions, and direct addressing instructions
optimized for built-in uses. Since each instruction is 16 bits long (some are 32 or 48
bits long), excellent memory efficiency is maintained. For details on the instructions,
see Appendix E, "Instruction List."
The instruction set can be divided into the following function groups:
Arithmetic operation
Load and store
Branch
Logical operation and bit operation
Direct addressing
Other
s Outline of Instructions
r Arithmetic operation
The standard arithmetic operation instructions (addition, deduction, and comparison) and shift
instructions (logical shift and arithmetic operation shift) belong to this group. For addition and
deduction, an operation function with carry is available for a multi-word operation instruction and
an operation function not changing the flag value is useful for an address calculation.
This group also includes multiplication instructions (32 bits
× 32 bits, 16 bits × 16 bits) and a
step division instruction (32 bits / 32 bits).
A immediate value transfer function for setting an immediate value in a register and an inter-
register transfer function are also provided.
All the arithmetic operation instructions are executed using the general-purpose and
multiplication/division registers in the CPU.
r Load and store
The load and store instructions are to read and write external memory. These instructions are
also used to read or write a peripheral circuit (I/O) in the chip. These instructions make byte
access, half-word access, or word access.
In addition to general indirect register memory
addressing, indirect register addressing with displacement or with register increment/decrement
are also available for some instructions.
r Branch
The branch, call, interrupt, and return instructions belong to this group. The branch instruction
may or may not have a delay slot for optimum application according to the use.
For details on the branch instruction, see 3.9.1, "Branch instruction with delay slot" and 3.9.2,
"Branch instruction without delay slot."