xi
13.4.2 Selection of Transfer Sequence ................................................................................................... 326
13.4.3 Addressing Mode .......................................................................................................................... 330
13.4.4 Transfer Data Selection ................................................................................................................ 331
13.4.5 Transfer Count Control ................................................................................................................. 332
13.4.6 CPU Control ................................................................................................................................. 333
13.4.7 DMA Transfer Start And Pause .................................................................................................... 335
13.4.8 Termination of DMA Transfer ....................................................................................................... 337
13.4.9 DMAC Interrupt Control ................................................................................................................ 339
13.4.10 DMA Channel Selection and Control ............................................................................................ 340
13.4.11 Supplemental Explanations on External Pins and Internal Operation Timings ............................ 342
13.5 Sample DMAC Transfer Program ...................................................................................................... 348
CHAPTER 14 BIT SEARCH MODULE ............................................................................ 351
14.1 Outline of the Bit Search Module ....................................................................................................... 352
14.2 Registers of the Bit Search Module ................................................................................................... 353
14.3 Bit Search Module Operations and Save/Restore Processing .......................................................... 355
CHAPTER 15 I-RAM/ROM ............................................................................................... 359
15.1 Outline of I-RAM/ROM ....................................................................................................................... 360
15.2 I-RAM Activation Sequence ............................................................................................................... 361
15.3 I-ROM/RAM Memory Mapping .......................................................................................................... 362
APPENDIX .......................................................................................................................... 365
APPENDIX A I/O Mapping ......................................................................................................................... 366
APPENDIX B Interrupt Vectors .................................................................................................................. 375
APPENDIX C Pin Status in Each CPU State .............................................................................................. 378
APPENDIX D Notes on Using Little Endian Area ....................................................................................... 385
D.1
Compiler (fcc911) ............................................................................................................................ 386
D.2
Assembler (fasm911) ...................................................................................................................... 389
D.3
Linker (flnk911) ............................................................................................................................... 391
D.4
Debugger (sim911, eml911, mon911) ............................................................................................. 392
APPENDIX E Instruction List ...................................................................................................................... 393
E.1
FR Series Instruction List ................................................................................................................ 399
INDEX ................................................................................................................................. 419