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7.5 8-bit PWM Timer Interrupts
7.5
8-bit PWM Timer Interrupts
The 8-bit PWM timer can generate an interrupt request when a match is detected
between the counter value and PWM compare register value for the interval timer
function. Interrupt requests are not generated for the PWM timer function.
8-bit PWM timer-1 generates the IRQ9 as an interrupt request and 8-bit PWM timer-2
generates the IRQA as an interrupt request.
s Interrupts for Interval Timer Function
The counter value is counted-up from "00H" on the selected count clock. When the counter
value matches the PWM compare register (COMR) value, the interrupt request flag bit (CNTR:
TIR) is set to "1".
At this time, an interrupt request (IRQ9, IRQA) to the CPU is generated if the interrupt request
enable bit is enabled (CNTR: TIE = "1"). Write "0" to the TIR bit in the interrupt processing
routine to clear the interrupt request.
The TIR bit is set to "1" when the counter value matches the set value, regardless of the value
of the TIE bit.
Note:
The TIR bit is not set if the counter is stopped (CNTR: TPE = "0") at the same time as the
counter value matches the COMR register value.
An interrupt request is generated immediately if the TIR bit is "1" when the TIE bit is changed
from disabled to enabled ("0" --> "1").
s Registers and Vector Tables for 8-bit PWM Timer Interrupts
Reference:
See Section 3.4.2 "Interrupt Processing" for details on the interrupt operation.
Table 7.5-1 Registers and Vector Tables for 8-bit PWM Timer Interrupts
Interrupt
Interrupt level setting register
Vector table address
Register
Setting bits
Upper
Lower
8-bit PWM Timer 1
IRQ9
ILR3 (007EH)
L91 (Bit3)
L90 (Bit2)
FFF8H
FFF9H
8-bit PWM Timer 2
IRQA
ILR3 (007EH)
LA1 (Bit5)
LA0 (Bit4)
FFF6H
FFF7H