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4.2 Port 0 and Port 1
4.2.1
Port-0 and Port-1 Registers (PDR0, PDR1, PURR0 DDR0,
DDR1, PURR1)
This section describes the port-0 and port-1 registers.
s Port-0 and Port-1 Register Functions
r Port 0, 1 data registers (PDR0, PDR1)
The PDR0 and PDR1 registers hold the pin states. Therefore, a bit corresponding to a pin set as
an output port can be read as the same state ("0" or "1" as the output latch, but when it is an
input port, it cannot be read as the output latch state.
Note:
For SETB and CLRB bit operation instructions, since the state of output latch (not the pin) is
read, the output latch states of bits other than those being operated on are not changed.
r Port 0, 1 data direction registers (DDR0, DDR1)
The DDR0 and DDR1 registers set the direction (input or output) for each pin (bit).
Setting "1" to the bit corresponding to a port (pin) sets the pin as an output port. Setting "0" sets
the pin as an input port.
Check:
As the DDR0 and DDR1 registers are write-only, the bit manipulation instructions (SETB and
CLRB) cannot be used.
r Settings when pins are used as external interrupt inputs
When port pins are used as external interrupt input pins, in addition to enabling the interrupt
circuit (external interrupt 1 or 2), the corresponding pins must also be set as inputs. (The
corresponding output latch data has no significance in this case.)
Table 4.2-3 "Port-0 and Port-1 Register Function" lists the functions of the port-0 and port-1
registers.
Table 4.2-3 Port-0 and Port-1 Register Function
Register
Data
Read
Write
Read/
Write
Address
Initial value
Port 0 data
register
(PDR0)
0Pin state is
the "L" level.
Sets "0" to the output latch.
Outputs an "L" level to the pin
if the pin functions as an
output port.
R/W
0000H
XXXXXXXXB
1Pin state is
the "H" level.
Sets "1" to the output latch.
Outputs an "H" level to the
pin if the pin functions as an
output port.