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参数资料
| 型号： | MB95F136TWPFV |
| 厂商： | FUJITSU LTD |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, FLASH, 10 MHz, MICROCONTROLLER, PDSO28 |
| 封装： | 8.60 X 17.75 MM, 2.80 MM HEIGHT, 1.27 MM PITCH, PLASTIC, SOP-28 |
| 文件页数： | 26/55页 |
| 文件大小： | 639K |
| 代理商： | MB95F136TWPFV |
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MB95130H Series
32
(2) Source Clock/Machine Clock
(VCC
= 5.0 V ± 10%, AVSS = VSS = 0.0 V, TA = 40 °C to + 85 °C)
*1 : Clock before setting division due to machine clock division ratio selection bit (SYCC : DIV1 and DIV0) . This
source clock is divided by the machine clock division ratio selection bit (SYCC : DIV1 and DIV0) , and it
becomes the machine clock. Further, the source clock can be selected as follows.
Main clock divided by 2
PLL multiplication of main clock (select from 1, 2, 2.5 multiplication)
Sub clock divided by 2
PLL multiplication of sub clock (select from 2, 3, 4 multiplication)
*2 : Operation clock of the microcontroller. Machine clock can be selected as follows.
Source clock (no division)
Source clock divided by 4
Source clock divided by 8
Source clock divided by 16
Parameter
Sym-
bol
Pin
name
Value
Unit
Remarks
Min
Typ
Max
Source clock cycle
time*1
(Clock before setting
division)
tSCLK
100
2000
ns
When using main clock
Min : FCH
= 10 MHz, PLL multiplied by 1
Max : FCH
= 1 MHz, divided by 2
7.6
61.0
s
When using subclock
Min : FCL
= 32 kHz, PLL multiplied by 4
Max : FCL
= 32 kHz, divided by 2
Source clock
frequency
FSP
0.5
10.0
MHz When using main clock
FSPL
16.384
131.072
kHz When using subclock
Machine clock cycle
time*2
(Minimum instruction
execution time)
tMCLK
100
32000
ns
When using main clock
Min : FSP
= 10 MHz, no division
Max : FSP
= 0.5 MHz, divided by 16
7.6
976.5
s
When using subclock
Min : FSPL
= 131 kHz, no division
Max : FSPL
= 16 kHz, divided by 16
Machine clock
frequency
FMP
0.031
10.000
MHz When using main clock
FMPL
1.024
131.072
kHz When using subclock
FCH
(main oscillation)
FCL
(sub oscillation)
Divided by 2
Main PLL
× 1
× 2
× 2.5
Divided by 2
Sub PLL
× 2
× 3
× 4
SCLK
(source clock)
Clock mode select bit
(SYCC: SCS1, SCS0)
MCLK
(machine clock)
Division
circuit
× 1
× 1/4
× 1/8
× 1/16
Outline of clock generation block
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