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参数资料
| 型号： | LTC3736EUF-1 |
| 厂商： | Linear Technology |
| 文件页数： | 6/28页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM CM 24-QFN |
| 标准包装： | 91 |
| 系列： | PolyPhase® |
| PWM 型： | 电流模式 |
| 输出数： | 2 |
| 频率 - 最大： | 825kHz |
| 占空比： | 100% |
| 电源电压： | 2.75 V ~ 9.8 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 24-WFQFN 裸露焊盘 |
| 包装： | 管件 |
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LTC3736-1
TYPICAL PERFOR A CE CHARACTERISTICS
T A = 25 ° C unless otherwise noted.
Shutdown Quiescent Current
vs Input Voltage
RUN/SS Start-Up Current
vs Input Voltage
20
18
16
14
RUN/SS = 0V
0.9
0.8
0.7
0.6
RUN/SS = 0V
12
10
8
6
4
2
0.5
0.4
0.3
0.2
0.1
0
2
3
4
5
6
7
8
9
10
0
2
3
4
5
6
7
8
9
10
INPUT VOLTAGE (V)
37361 G17
INPUT VOLTAGE (V)
37361 G18
PI FU CTIO S
(UF/GN Package)
I TH1 /I TH2 (Pins 1, 8/Pins 4, 11): Current Threshold and
Error Amplifier Compensation Point. Nominal operating
range on these pins is from 0.7V to 2V. The voltage on
these pins determines the threshold of the main current
comparator.
FREQ (Pin 3/Pin 6): Frequency Filter and Adjust Pin. Nor-
mally, when spread spectrum operation is enabled (SSDIS
= GND), a capacitor (1nF to 4.7nF) is connected from this
pin to SGND or V IN to filter and smooth the changes in fre-
quency of the LTC3736-1’s internal oscillator.
When spread spectrum operation is disabled (SSDIS = V IN ),
this pin serves as a frequency adjust pin. In this mode, tying
this pin to GND selects 300kHz operation; tying this pin to
V IN selects 750kHz operation; floating this pin selects
550kHz operation.
When spread spectrum operation is enabled (SSDIS =
GND), an external voltage between approximately 0.7V and
1.5V may be applied to this pin to adjust (in an analog
manner) the LTC3736-1’s frequency.
SGND (Pin 4/Pin 7): Small-Signal Ground. This pin serves
as the ground connection for most internal circuits.
V IN (Pin 5/Pin 8): Chip Signal Power Supply. This pin
powers the entire chip except for the gate drivers. Externally
filtering this pin with a lowpass RC network (e.g.,
R = 10 ? , C = 1 μ F) is suggested to minimize noise pickup,
especially in high load current applications.
TRACK (Pin 6/Pin 9): Tracking Input for Second Control-
ler. Allows the start-up of V OUT2 to “track” that of V OUT1
according to a ratio established by a resistor divider on
V OUT1 connected to the TRACK pin. For one-to-one track-
ing of V OUT1 and V OUT2 during start-up, a resistor divider
with a ratio equal to those connected to V FB2 from V OUT2
should be used to connect to TRACK from V OUT1 .
PGOOD(Pin 9/Pin 12): Power Good Output Voltage Moni-
tor Open-Drain Logic Output. This pin is pulled to ground
when the voltage on either feedback pin (V FB1 , V FB2 ) is not
within ± 13.3% of its nominal set point.
PGND (Pins 12, 16, 20, 25/Pins 15, 19, 23): Power Ground.
These pins serve as the ground connection for the gate
drivers and the negative input to the reverse current com-
parators. The Exposed Pad (UF package) must be soldered
to PCB ground.
RUN/SS (Pin 14/Pin 17): Run Control Input and Optional
External Soft-Start Input. Forcing this pin below 0.65V shuts
down the chip (both channels). Driving this pin to V IN or
releasing this pin enables the chip, using the chip’s inter-
nal soft-start. An external soft-start can be programmed by
connecting a capacitor between this pin and ground.
37361f
6
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