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参数资料
| 型号： | MC12430FA |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 800 MHz, OTHER CLOCK GENERATOR, PQFP32 |
| 封装： | PLASTIC, LQFP-32 |
| 文件页数： | 11/12页 |
| 文件大小： | 503K |
| 代理商： | MC12430FA |
MC12430
8
MOTOROLA
Power Supply Filtering
The MC12430 is a mixed analog/digital product and as
such it exhibits some sensitivities that would not necessarily
be seen on a fully digital product. Analog circuitry is naturally
susceptible to random noise, especially if this noise is seen on
the power supply pins. The MC12430 provides separate
power supplies for the digital circuitry (VCC) and the internal
PLL (PLL_VCC) of the device. The purpose of this design
technique is to try and isolate the high switching noise digital
outputs from the relatively sensitive internal analog
phase–locked loop. In a controlled environment such as an
evaluation board, this level of isolation is sufficient. However,
in a digital system environment where it is more difficult to
minimize noise on the power supplies a second level of
isolation may be required. The simplest form of isolation is a
power supply filter on the PLL_VCC pin for the MC12430.
Figure 6 illustrates a typical power supply filter scheme.
The MC12430 is most susceptible to noise with spectral
content in the 1KHz to 1MHz range. Therefore, the filter should
be designed to target this range. The key parameter that
needs to be met in the final filter design is the DC voltage drop
that will be seen between the VCC supply and the PLL_VCC
pin of the MC12430. From the data sheet, the IPLL_VCC current
(the current sourced through the PLL_VCC pin) is typically
15mA (20mA maximum), assuming that a minimum of 3.0 V
must be maintained on the PLL_VCC pin, very little DC
voltage drop can be tolerated when a 3.3 V VCC supply is
used. The resistor shown in Figure 6 must have a resistance
of 10–15
to meet the voltage drop criteria. The RC filter
pictured will provide a broadband filter with approximately
100:1 attenuation for noise whose spectral content is above
20KHz. As the noise frequency crosses the series resonant
point of an individual capacitor its overall impedance begins to
look inductive and thus increases with increasing frequency.
The parallel capacitor combination shown ensures that a low
impedance path to ground exists for frequencies well above
the bandwidth of the PLL.
Figure 6. Power Supply Filter
PLL_VCC
VCC
MC12430
0.01 F
22 F
0.01 F
3.3 V or
5.0 V
RS=10-15
A higher level of attenuation can be achieved by replacing
the resistor with an appropriate valued inductor. A 1000
H
choke will show a significant impedance at 10 KHz
frequencies and above. Because of the current draw and the
voltage that must be maintained on the PLL_VCC pin, a low
DC resistance inductor is required (less than 15
). Generally,
the resistor/capacitor filter will be cheaper, easier to implement
and provide an adequate level of supply filtering.
The MC12430 provides sub–nanosecond output edge
rates and thus a good power supply bypassing scheme is a
must. Figure 7 shows a representative board layout for the
MC12430. There exists many different potential board layouts
and the one pictured is but one. The important aspect of the
layout in Figure 7 is the low impedance connections between
VCC and GND for the bypass capacitors. Combining good
quality general purpose chip capacitors with good PCB layout
techniques will produce effective capacitor resonances at
frequencies adequate to supply the instantaneous switching
current for the 12430 outputs. It is imperative that low
inductance chip capacitors are used; it is equally important
that the board layout does not introduce back all of the
inductance saved by using the leadless capacitors. Thin
interconnect traces between the capacitor and the power
plane should be avoided and multiple large vias should be
used to tie the capacitors to the buried power planes. Fat
interconnect and large vias will help to minimize layout
induced inductance and thus maximize the series resonant
point of the bypass capacitors.
Figure 7. PCB Board Layout for MC12430 (28 PLCC)
C2
1
C3
R1
Xtal
C1
R1 = 10-15
C1 = 0.01F
C2 = 22F
C3 = 0.01F
= VCC
= GND
= Via
Note the dotted lines circling the crystal oscillator
connection to the device. The oscillator is a series resonant
circuit and the voltage amplitude across the crystal is relatively
small. It is imperative that no actively switching signals cross
under the crystal as crosstalk energy coupled to these lines
could significantly impact the jitter of the device. Special
attention should be paid to the layout of the crystal to ensure a
stable, jitter free interface between the crystal and the
on–board oscillator.
Although the MC12430 has several design features to
minimize the susceptibility to power supply noise (isolated
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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MC12430
High Frequency Clock Synthesizer
NETCOM
IDT High Frequency Clock Synthesizer
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MC12430
8
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相关代理商/技术参数 |
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|---|---|
| MC12430FN | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:HIGH FREQUENCY PLL CLOCK GENERATOR |
| MC12439 | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:HIGH FREQUENCY PLL CLOCK GENERATOR |
| MC12439FN | 制造商:Motorola Inc 功能描述: 制造商:Motorola Inc 功能描述:MISCELLANEOUS CLOCK GENERATOR, 28 Pin, Plastic, PLCC |
| MC1243F | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MC1245L | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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