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参数资料
| 型号： | ATF750C-7PC |
| 厂商： | Atmel |
| 文件页数： | 4/25页 |
| 文件大小： | 0K |
| 描述： | IC CPLD 7NS 24DIP |
| 标准包装： | 15 |
| 系列： | ATF750C(L) |
| 可编程类型： | 系统内可编程（最少 1K 次编程/擦除循环） |
| 最大延迟时间 tpd(1)： | 7.5ns |
| 电压电源 - 内部： | 4.75 V ~ 5.25 V |
| 宏单元数： | 10 |
| 输入/输出数： | 10 |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 通孔 |
| 封装/外壳： | 24-DIP（0.300"，7.62mm） |
| 供应商设备封装： | 24-PDIP |
| 包装： | 管件 |
| 其它名称： | ATF750C7PC |
12
0776L–PLD–11/08
ATF750C(L)
23. Using the ATF750C’s Many Advanced Features
The ATF750C(L)’s advanced flexibility packs more usable gates into 24 pins than any other logic
device. The ATF750C(L)s start with the popular 22V10 architecture, and add several enhanced
features:
Selectable D- and T-type Registers
Each ATF750C(L) flip-flop can be individually configured as either D- or T-type. Using the T-
type configuration, JK and SR flip-flops are also easily created. These options allow more
efficient product term usage.
Selectable Asynchronous Clocks
Each of the ATF750C(L)’s flip-flops may be clocked by its own clock product term or directly
from Pin 1 (SMD Lead 2). This removes the constraint that all registers must use the same
clock. Buried state machines, counters and registers can all coexist in one device while
running on separate clocks. Individual flip-flop clock source selection further allows mixing
higher performance pin clocking and flexible product term clocking within one design.
A Full Bank of Ten More Registers
The ATF750C(L) provides two flip-flops per output logic cell for a total of 20. Each register
has its own sum term, its own reset term and its own clock term.
Independent I/O Pin and Feedback Paths
Each I/O pin on the ATF750C(L) has a dedicated input path. Each of the 20 registers has its
own feedback terms into the array as well. This feature, combined with individual product
terms for each I/O’s output enable, facilitates true bi-directional I/O design.
24. Synchronous Preset and Asynchronous Reset
One synchronous preset line is provided for all 20 registers in the ATF750C(L). The appropriate
input signals to cause the internal clocks to go to a high state must be received during a syn-
chronous preset. Appropriate setup and hold times must be met, as shown in the switching
waveform diagram.
An individual asynchronous reset line is provided for each of the 20 flip-flops. Both master and
slave halves of the flip-flops are reset when the input signals received force the internal resets
high.
25. Software Support
All family members of the ATF750C(L) can be designed with Atmel
-WinCUPL.
Additionally, the ATF750C may be programmed to perform the ATV750(L) functional subset (no
T-type flip-flops, pin clocking or D/T2 feedback) using the ATV750 JEDEC file. In this case, the
ATF750C becomes a direct replacement or speed upgrade for the ATV750. The ATF750C is a
direct replacement for the ATV750(L) and the ATV750B(L).
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