参数资料
型号: MC56F8355MFGE
厂商: Freescale Semiconductor
文件页数: 7/172页
文件大小: 0K
描述: IC DSP 16BIT 60MHZ 128-LQFP
标准包装: 72
系列: 56F8xxx
核心处理器: 56800E
芯体尺寸: 16-位
速度: 60MHz
连通性: CAN,EBI/EMI,SCI,SPI
外围设备: POR,PWM,温度传感器,WDT
输入/输出数: 49
程序存储器容量: 264KB(132K x 16)
程序存储器类型: 闪存
RAM 容量: 10K x 16
电压 - 电源 (Vcc/Vdd): 2.25 V ~ 3.6 V
数据转换器: A/D 16x12b
振荡器型: 外部
工作温度: -40°C ~ 125°C
封装/外壳: 128-LQFP
包装: 托盘
配用: MC56F8367EVME-ND - EVAL BOARD FOR MC56F83X
56F8355 Technical Data, Rev. 17
104
Freescale Semiconductor
Preliminary
Part 6 System Integration Module (SIM)
6.1 Overview
The SIM module is a system catchall for the glue logic that ties together the system-on-chip. It controls
distribution of resets and clocks and provides a number of control features. The system integration module
is responsible for the following functions:
Reset sequencing
Clock generation & distribution
Stop/Wait control
Pullup enables for selected peripherals
System status registers
Registers for software access to the JTAG ID of the chip
Enforcing Flash security
These are discussed in more detial in the sections that follow.
6.2 Features
The SIM has the following features:
Flash security feature prevents unauthorized access to code/data contained in on-chip Flash memory
Power-saving clock gating for peripheral
Three power modes (Run, Wait, Stop) to control power utilization
— Stop mode shuts down the 56800E core, system clock, peripheral clock, and PLL operation
— Stop mode entry can optionally disable PLL and Oscillator (low power vs. fast restart); must be
explicitly done
— Wait mode shuts down 56800E core and unnecessary system clock operation
— Run mode supports full part operation
Controls to enable/disable the 56800E core WAIT and STOP instructions
Calculates base delay for reset extension based upon POR or RESET operations. Reset delay will be 3 x 32
clocks (phased release of reset) for reset, except for POR, which is 221 clock cycles.
Controls reset sequencing after reset
Software-initiated reset
Four 16-bit registers reset only by a Power-On Reset usable for general-purpose software control
System Control Register
Registers for software access to the JTAG ID of the chip
6.3 Operating Modes
Since the SIM is responsible for distributing clocks and resets across the chip, it must understand the
various chip operating modes and take appropriate action. These are:
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