Serial Management Controllers (SMCs)
MC68360 USER’S MANUAL
Bits 7, 5, 3—Reserved.
BRKe—Break End
The end of break sequence was detected. This indication will be no sonner than after one
idle bit is received following a break sequence.
BRK—Break Character Received
A break character was received. If a very long break sequence occurs, this interrupt will
occur only once after the first all-zeros character is received.
BSY—Busy Condition
A character was received and discarded due to lack of buffers. This bit is be set no sooner
than the middle of the last stop bit of the first receive character for which there is no avail-
able buffer. Reception continues when an empty buffer is provided.
TX—Tx Buffer
A buffer has been transmitted over the UART channel. This bit is set once the transmit
data of the last character in the buffer was written to the transmit FIFO. The user must wait
two character times to be sure that the data was completely sent over the transmit pin.
RX—Rx Buffer
A buffer has been received and its associated Rx BD is now closed. This bit is set no soon-
er than the middle of the last stop bit of the last character that was written to the receive
buffer.
Figure 7-77. SMC UART Interrupts Example
LINE IDLE
10 CHARACTERS
CHARACTERS
RECEIVED BY SMC UART
TIME
RXD
LINE IDLE
7 CHARACTERS
LINE IDLE
TXD
RX
TX
BREAK
BRK
NOTES:
1. The first RX event assumes receive buffers are six bytes each.
2. The second RX event position is programmable based on the max_IDL value.
3. The BRK event occurs after the first break character is received.
NOTE: The TX event assumes all seven characters were put into a single buffer, and the TX event occurred when the seventh
character was written to the SMC transmit FIFO.
SMC UART SMCE
EVENTS
CHARACTERS
TRANSMITTED BY SMC UART
SMC UART SMCE
EVENTS
BRKe
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Freescale Semiconductor, Inc.
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